Glass Core Package Substrate With Embedded Bridge Die to Prevent Warpage
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Solution Overview
Problem
Conventional 2.5D semiconductor packages face challenges in reducing size due to vertical stack structures and suffer from power loss and warpage due to differences in thermal expansion coefficients between components.
Innovation Solution
A package substrate with a glass core layer and bridge die structure, using organic and inorganic dielectric materials for ultra-high-density connections, eliminates the need for printed circuit boards and interposers, allowing for a more compact design and efficient power transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a vertical stack structure of printed circuit board, interposer, and semiconductor dies is used, then electrical connection between fine pitch and normal pitch is achieved, but package size in vertical direction cannot be reduced
Solution Approach 1:
The patent transitions from a vertical stack structure to a planar arrangement by forming a cavity in the substrate and disposing the bridge die within this cavity. This dimensional change allows components to be arranged in the horizontal plane rather than stacking vertically, thereby reducing package height and overall volume while maintaining electrical connection functionality.
Solution Approach 2:
The bridge die is nested within the cavity formed in the substrate, allowing it to be embedded rather than stacked on top. This nesting approach integrates the bridge die into the substrate structure itself, reducing the overall package volume by eliminating the need for separate vertical stacking of interposer and semiconductor dies.
2Reliability
If conventional molding materials are used to cover semiconductor dies, then protection is provided, but warpage occurs due to differences in coefficient of thermal expansion
Solution Approach 1:
The patent changes the material parameter of the substrate from conventional organic materials to glass material, which has a coefficient of thermal expansion matched to silicon-based semiconductor dies. This parameter change eliminates thermal expansion mismatches that cause warpage during molding and operation, while still providing the necessary protection and structural support.
Solution Approach 2:
The use of glass substrate with matched thermal expansion coefficient creates homogeneity in thermal behavior across different components (substrate, bridge die, and semiconductor dies). This homogeneous thermal response prevents differential expansion and contraction, eliminating warpage issues while maintaining protective enclosure.
3Power
If power is transferred through semiconductor dies in conventional 2.5D packages, then electrical connection is achieved, but power loss occurs on the transfer path
Solution Approach 1:
The patent extracts the power transfer function from the semiconductor dies themselves and relocates it to dedicated power transfer paths formed in the glass substrate. By separating power transfer from signal processing functions, power can be delivered efficiently through optimized conductive paths rather than through the computational logic of the dies, reducing power loss.
Solution Approach 2:
The glass substrate with embedded conductive power transfer paths acts as an intermediary between power sources and semiconductor dies. This intermediary structure provides dedicated low-resistance pathways for power delivery, separating the power transfer function from the signal processing function and minimizing power loss on the transfer path.
Data Source
AI summary
A package substrate according to an embodiment may include a substrate that includes a core layer that includes a first region and a second region, a surface of the second region being recessed from a surface of the first region, and a first redistribution layer on the first region, the first redistribution layer including a first organic dielectric and a plurality of first circuit wiring lines inside the first organic dielectric, and a bridge die that is disposed on the second region and includes a connection layer that includes a glass bridge base and a plurality of wiring lines inside the glass bridge base, and a second redistribution layer on the connection layer, the second redistribution layer including an inorganic dielectric and a plurality of second circuit wiring lines inside the inorganic dielectric.