Glass-Core Thin Film Capacitor Architecture for High-Voltage Packaging
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Solution Overview
Problem
Existing capacitor structures for semiconductor packaging applications are limited in their ability to operate at high frequencies and high voltages due to breakdown concerns and are often far from the computing die, with metal-insulator-metal (MIM) capacitors being restricted to low voltage applications due to leakage issues.
Innovation Solution
Integration of thin film capacitors (TFCs) into package substrates, utilizing a glass core with laser-assisted patterning to create cavities and through-glass vias, and employing a corrugated architecture or photoimageable dielectric scaffolding to increase capacitance density, with a TFC stack comprising workfunction metals and high dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If land-side ceramic capacitors or die-side ceramic capacitors are used, then capacitance is provided, but they cannot operate at high voltages due to breakdown concerns and are relatively far from the computing die
Solution Approach 1:
The patent transitions from planar capacitor layouts (land-side or die-side) to a three-dimensional architecture where capacitors are formed within through-glass vias. This vertical integration into the substrate thickness dimension enables high voltage operation through increased breakdown distance while maintaining proximity to the computing die through direct vertical connection paths.
Solution Approach 2:
The capacitor structure is nested within the through-glass via structure, with capacitor plates formed on the sidewalls of the via cavity. This nesting approach allows the capacitor to be embedded within the substrate volume rather than occupying separate planar space, simultaneously achieving compact integration near the die and sufficient voltage breakdown distance through the via depth.
2Quantity of substance
If on-die metal insulator metal (MIM) capacitors are used, then capacity density is achieved, but leakage occurs due to thin dielectric films limiting them to low voltage applications
Solution Approach 1:
The patent changes the dielectric thickness parameter from thin films used in on-die MIM capacitors to substantially thicker dielectric layers in the through-glass via capacitors. This parameter change increases the breakdown voltage capability while maintaining high capacitance density through the increased surface area provided by the via sidewalls and the high dielectric constant materials used.
3Reliability
If through-glass vias with capacitor structures are formed, then high voltage and high frequency operation is enabled, but manufacturing complexity increases due to laser-assisted patterning and multi-layer formation
Solution Approach 1:
The patent replaces conventional mechanical drilling or etching methods for creating through-glass vias with laser-assisted patterning. This substitution enables precise formation of complex via geometries and integrated capacitor structures in a single process step, reducing overall manufacturing complexity despite the advanced functionality achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-frequency and high-voltage operations while maintaining proximity to computing dies, enhancing capacitance density without increasing footprint, thus addressing the limitations of existing capacitor structures.
Implementation Method 1
utilizing a glass core with laser-assisted patterning to create cavities and through-glass vias
Data Source
AI summary
Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.