Package Carrier with Glass Interposer for Conductive Performance
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Solution Overview
Problem
Current embedded passive substrates have limitations in connectivity, leading to poor conductivity and reliability due to single-sided wiring, small contact areas, and material-induced warpage, which affects chip packaging yield and structural rigidity.
Innovation Solution
A package carrier design featuring a substrate with interposers, conductive structure layers, and build-up structures on both surfaces, eliminating blind vias and providing improved coplanarity, rigidity, and conductive performance through a glass substrate with conductive vias and pads connected to patterned circuit layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive blind holes are used to connect passive components to substrate, then connectivity is achieved, but conductivity deteriorates due to multiple connection interfaces and small contact area
Solution Approach 1:
The patent divides the connection structure into separate surface-mounted pads on the substrate that directly contact the passive components, eliminating the need for blind vias. This segmentation approach creates dedicated contact areas on the surface, improving conductivity by removing intermediate connection interfaces while maintaining connectivity through direct pad-to-component contact.
Solution Approach 2:
The patent transitions from three-dimensional blind via connections (through-substrate holes) to two-dimensional surface-mounted pad connections. By moving the connection interface to the substrate surface, the design eliminates the depth-related conductivity issues of blind vias while providing larger contact areas, thus improving conductive performance without the complexity of multiple interfaces.
2Ease of manufacture
If copper-foil substrates are used, then ease of manufacture is improved, but coplanarity deteriorates due to material warpage
Solution Approach 1:
The patent changes the material parameter of the substrate from copper-foil based to a warpage-resistant material composition. This parameter change eliminates the thermal expansion and warping issues inherent in copper-foil substrates, providing improved coplanarity across the substrate surface while maintaining manufacturability through standard fabrication processes adapted to the new material composition.
Solution Approach 2:
The patent employs a composite substrate structure with specific material layers designed to resist warpage. By using composite materials with balanced thermal and mechanical properties, the substrate maintains flatness and coplanarity during manufacturing and operation, solving the warpage issue while remaining compatible with conventional manufacturing techniques.
3Device complexity
If single-sided wiring layout is used, then device complexity is reduced, but adaptability deteriorates as wires cannot be laid on the back of passive components
Solution Approach 1:
The patent utilizes both surfaces of the substrate for wiring and component placement by providing pad structures on the first surface and corresponding connection areas on the second surface. This two-dimensional utilization of substrate surfaces enables wires to be laid on both the front and back of passive components, significantly improving adaptability and versatility while maintaining relatively simple wiring layouts through systematic pad placement.
Data Source
AI summary
A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.