Glass Substrate Semiconductor Structures with Polymer Thermal Expansion Matching
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Solution Overview
Problem
Existing circuit boards are not entirely satisfactory for semiconductor chip integration due to limitations in electrical performance and compatibility with advanced semiconductor technologies, particularly in terms of integration density and thermal expansion matching.
Innovation Solution
A method of forming a semiconductor structure on a glass substrate with multiple conductive layers and polymer layers, where metal features and vias are electroplated and embedded in polymer layers with adjustable thermal expansion coefficients to enhance electrical performance and reduce warpage, and the glass substrate is bonded to other carriers or frames for further integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional circuit boards are used for semiconductor chip integration, then manufacturing simplicity is maintained, but electrical performance and thermal expansion matching are insufficient
Solution Approach 1:
The patent employs a composite structure consisting of a glass substrate combined with multiple polymer layers (first polymer layer and second polymer layer) having different properties. This composite material approach enables simultaneous achievement of improved electrical performance through the glass substrate and adjustable thermal expansion coefficients through the polymer layer selection, while maintaining manufacturing simplicity by using sequential lamination processes
Solution Approach 2:
The patent utilizes parameter changes by selecting polymer layers with specific thermal expansion coefficients that match those of semiconductor chips. By changing the material parameters of the polymer layers to match the thermal expansion characteristics of the chips, the invention resolves the thermal expansion matching issue while maintaining the structural integrity and electrical performance of the overall assembly
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by providing different polymer layers with distinct properties at different locations and functions within the assembly. The first polymer layer encapsulates the semiconductor chip with specific thermal expansion matching properties, while the second polymer layer provides additional encapsulation and structural support. This localized differentiation enables precise control over thermal and mechanical properties in different regions, supporting high integration density while maintaining manufacturing precision
Solution Approach 2:
The patent segments the encapsulation structure into multiple distinct polymer layers, each performing specific functions. The first polymer layer is dedicated to thermal expansion matching and chip encapsulation, while the second polymer layer provides additional protection and structural integrity. This segmentation allows each layer to be optimized for its specific function, enabling high precision manufacturing even at reduced feature sizes
3Reliability
If glass substrate with multiple polymer layers is used, then electrical performance and thermal expansion matching are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-selecting and preparing polymer layers with specific thermal expansion coefficients before the assembly process. The first and second polymer layers are chosen in advance to match the thermal expansion characteristics of the semiconductor chip, eliminating the need for complex post-assembly adjustments. This preliminary preparation simplifies the overall manufacturing process while ensuring optimal thermal expansion matching
Solution Approach 2:
The patent uses polymer layers as intermediary materials between the glass substrate and the semiconductor chip. These intermediary polymer layers serve as thermal expansion buffers that match the chip's thermal characteristics, mediating the thermal stresses between components. This intermediary approach simplifies the manufacturing process by providing a straightforward lamination sequence while achieving complex thermal management objectives
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor structure with improved electrical performance, reduced size, and adjustable thermal expansion properties, addressing the limitations of conventional circuit boards and simplifying the integration process while reducing yield loss and production costs.
Implementation Method 1
metal features and vias are electroplated and embedded in polymer layers
Implementation Method 2
embedded in polymer layers with adjustable thermal expansion coefficients to enhance electrical performance and reduce warpage
Implementation Method 3
the glass substrate is bonded to other carriers or frames for further integration
Data Source
AI summary
A method of forming a semiconductor structure includes the following operations. A first conductive structure is formed on a first side of a first glass carrier. A second glass carrier is bonded to the first conductive structure. Conductive vias are formed to penetrate through the first glass carrier, and the conductive vias are electrically connected to the first conductive structure. A second conductive structure is formed on a second side of the first glass carrier opposite to the first side, and the second conductive structure is electrically connected to the conductive vias.