Glitch Detection Circuit for Clock Signal Integrity
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Solution Overview
Problem
Integrated circuits (ICs) face issues with clock signal distortion due to noise and interference, leading to glitches that can degrade Phase Locked Loop (PLL) performance and cause PLL unlocking.
Innovation Solution
A glitch detection circuit is introduced, comprising an edge detector, a delayed-pulse generator, and a glitch identifier. This circuit generates pulse signals in response to clock signal edges and identifies glitches based on predetermined pulse signal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glitch detection circuit is added to monitor clock signal integrity, then PLL reliability is improved, but device complexity increases
Solution Approach 1:
The glitch detection circuit is segmented into three functional modules: an edge detector that generates pulse signals for rising and falling edges, a delayed-pulse generator that creates time-shifted versions of these pulses, and a glitch identifier that compares the delayed pulses with the clock signal. This segmentation allows each module to perform a specific function, improving detection reliability while keeping the overall implementation manageable through modular design.
2Measurement precision
If pulse signal duration is extended to improve glitch detection accuracy, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The circuit uses periodic pulse generation synchronized with the clock signal edges. The delayed-pulse generator creates pulses at predetermined time intervals after edge detection, and the glitch identifier samples the clock signal at these periodic intervals. This periodic action allows sufficient time for accurate comparison while maintaining synchronization with the clock rhythm, balancing detection accuracy with time efficiency.
3Measurement precision
If the detection threshold is made more sensitive to detect subtle glitches, then measurement precision is improved, but object-affected harmful factors increase
Solution Approach 1:
The delayed-pulse generator acts as an intermediary mechanism that introduces a predetermined time delay between edge detection and the comparison operation. This delay allows transient noise to settle while preserving genuine glitch characteristics. The intermediary timing mechanism enables the glitch identifier to distinguish between brief noise spikes and actual glitches, improving sensitivity without increasing false positives.
Data Source
AI summary
Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and/or based on the fourth pulse signal having the same logical level as the clock signal.