Glitch Power Analysis in Digital Circuit Simulation Vectors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital integrated circuit design tools struggle to accurately estimate power consumption, particularly due to the increasing significance of glitch power, which can account for up to 50% of total power consumption, leading to under or overestimation of power requirements and resulting in inefficient designs and increased manufacturing costs.
Innovation Solution
A method and system for identifying and categorizing glitch transitions in simulation vectors, using clock cycle-based analysis to compute glitch power consumption by differentiating between inertial and transport glitches, and providing feedback for design optimization through glitch-aware data formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If glitch power is not analyzed, then design turnaround time is reduced, but power consumption accuracy deteriorates
Solution Approach 1:
The patent performs glitch power analysis during the simulation phase, before final design implementation. By analyzing glitch transitions in simulation vectors and computing glitch power consumption using the formula P_glitch = α × C × V² × f × N_glitch, the system obtains accurate power estimates early in the design process, enabling power optimization without extending the overall design timeline
Solution Approach 2:
The patent introduces an intermediary analysis layer that processes simulation vectors to extract glitch transitions. This intermediary step identifies glitch events by detecting multiple transitions within a clock period, categorizes them as inertial or transport glitches, and computes their power contribution separately from regular switching activity, thereby providing accurate power estimates without requiring additional simulation runtime
2Measurement precision
If detailed glitch analysis is performed, then power consumption accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent segments the power analysis into distinct components: regular switching power and glitch power. By separating glitch detection from general power analysis, the system processes only transitions that qualify as glitches (multiple transitions per clock period), categorizing them into inertial glitches (filtered by slew rate) and transport glitches. This segmentation reduces computational overhead by focusing analysis only on relevant transitions rather than analyzing all signal activity
Solution Approach 2:
The patent introduces specific parameters for glitch characterization, including pulse width calculation (difference between transition timestamps), average slew computation, and glitch scaling ratios. These parameter changes enable differentiated power computation for inertial versus transport glitches, with inertial glitches applying a derating factor based on the ratio of pulse width to average slew, thereby achieving accurate power measurement through targeted parameter analysis rather than exhaustive computational methods
3Manufacturing precision
If inertial glitches are differentiated from transport glitches, then power optimization precision is improved, but analysis complexity increases
Solution Approach 1:
The patent applies different analysis criteria and power computation methods to different types of glitches based on their local characteristics. Inertial glitches (with pulse width less than average slew) are derated using a scaling ratio, while transport glitches (with pulse width greater than or equal to average slew) are treated differently. This local quality approach enables precise power optimization for each glitch type according to its specific behavior, allowing targeted optimization without requiring complex unified analysis methods
Data Source
AI summary
A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.