Global Bit Line Pre-charge Circuit for PVT Compensation
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Solution Overview
Problem
Flash memory technologies face limitations in scaling due to the wear-out of thin tunnel dielectric layers in floating gate transistors, leading to reduced program/erase cycles and data retention issues, and require additional operations like erase before write and multiple terminals for data access.
Innovation Solution
The development of two-terminal cross-point memory arrays using discrete re-writeable non-volatile memory elements, such as conductive metal oxide-based memory elements, which allow for high-capacity storage without the need for erase operations before write and can be vertically stacked for increased density, utilizing a semiconductor substrate for control circuitry and memory layers formed above for efficient data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If floating gate transistors are scaled down to increase memory capacity, then memory density is improved, but the thin tunnel dielectric layer wears out faster reducing program/erase cycles
Solution Approach 1:
The patent segments the memory cell structure by replacing the traditional floating gate transistor with a charge trap memory element that uses separate trap regions for charge storage. This segmentation allows the memory element to achieve high density without the wear-out problems of scaled floating gate transistors, as the trap regions can be engineered to withstand more program/erase cycles.
Solution Approach 2:
The patent changes the fundamental parameter of charge storage mechanism by transitioning from floating gate transistors to charge trap memory elements with trap regions. This parameter change enables the memory to maintain reliability at high densities by using material properties and trap depth engineering rather than relying on scaled transistor geometries.
2Reliability
If Flash memory requires erase operation before write operation, then data integrity is improved, but write latency increases
Solution Approach 1:
The patent implements preliminary action by pre-charging the global bit line to a specific voltage level before write operations. This preliminary voltage setup eliminates the need for full erase operations before writes, as the pre-charged state provides sufficient margin for reliable data writing while maintaining data integrity through controlled charge injection into the trap regions.
Solution Approach 2:
The patent introduces dynamic voltage control where the global bit line voltage is dynamically adjusted based on the operation type (read, write, verify). During write operations, the GBL is pre-charged to an optimized voltage that enables direct programming without full erase, dynamically optimizing the write path to reduce latency while maintaining reliability through voltage-controlled charge injection.
3Adaptability or versatility
If multiple terminals are used for data access in Flash memory, then control capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates unnecessary terminals by using a two-terminal memory element structure instead of the three-terminal floating gate transistor. The charge trap memory element achieves full control capability with only two terminals (word line and bit line), taking out the redundant terminal from the traditional structure while maintaining adaptability for various memory operations through clever voltage application sequences.
Data Source
AI summary
A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.