Global Test Generators for Inter Cluster Defect Detection

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Solution Overview

Problem

Existing testing architectures for multi-die packages are limited in their ability to detect inter cluster defects, which are defects that span between two clusters, as they primarily focus on intra cluster defects.

Innovation Solution

The implementation of a global test signal generator and a global expected response generator allows for parallel testing of multiple clusters, enabling the detection of inter cluster defects by testing neighboring clusters simultaneously.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If testing is carried out at a cluster level with sequential lane testing, then intra cluster defects can be detected, but inter cluster defects are not detectable

Engineering Contradiction:

Improvedefect detection capabilityVSAvoidtesting coverage scope

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The testing architecture is segmented into multiple independent test channels, each capable of testing a specific lane in parallel. This segmentation allows the system to simultaneously test multiple clusters across different boundaries, enabling detection of inter cluster defects while maintaining the ability to detect intra cluster defects.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple test channels are merged into a unified testing system that operates in parallel. The test generator and response analyzer are combined to create a coordinated multi-channel testing architecture that can simultaneously monitor multiple clusters, thereby detecting both intra cluster and inter cluster defects.

Inventive Principle:

Principle #5Merging (Combining)

2Device complexity

If traditional cluster-level testing is used, then testing architecture is simple, but inter cluster defects cannot be detected

Engineering Contradiction:

Improvetesting architecture complexityVSAvoidmulti-die module yield

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The test generator proactively generates test patterns for multiple lanes simultaneously before defects can manifest during operation. This preliminary testing action identifies potential inter cluster defects early in the manufacturing process, improving reliability without requiring complex operational monitoring systems.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The response analyzer provides feedback on the actual signal responses from multiple clusters simultaneously. This feedback mechanism compares expected versus actual responses to identify defects in both intra cluster and inter cluster connections, improving yield through early defect detection.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250068529A1Test and repair architecture for inter and intra cluster defects

Publication Date: 2025.02.27 INTEL CORP

AI summary

Embodiments disclosed herein include apparatuses for improved testing between chips. In an embodiment, an apparatus comprises a plurality of transmit clusters on a first chip, where individual ones of the plurality of transmit clusters comprise a set of transmit lanes on the first chip. In an embodiment, a plurality of finite state machines (FSMs) are on the first chip, where individual ones of the plurality of transmit clusters comprise one of the plurality of FSMs. In an embodiment, a global transmit test generator is communicatively coupled to each of the set of transmit lanes on the first chip, and a global transmit expected response generator is communicatively coupled to each of the plurality of FSMs on the first chip.