GOA Region Wiring via Third Metal Layer for Narrow Frame
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Solution Overview
Problem
The existing Gate Driver on Array (GOA) technology in TFT-LCDs faces challenges in achieving a narrow-frame design due to large spacing between metal wires, which increases the risk of short circuits and limits the design's narrowness, as well as the difficulty in maintaining adequate space between wires to prevent intersections.
Innovation Solution
The implementation of a third patterned metal layer with through holes connecting the first and second patterned metal layers in the GOA region, reducing the area occupied by wiring and allowing for closer spacing of metal wires, thereby minimizing the risk of short circuits and enabling a narrower frame design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal wires are disposed in two layers in the GOA region, then the gate driver can be fabricated directly on the array substrate, but the space between metal wires must be large to avoid short circuits, resulting in a large width of the GOA region
Solution Approach 1:
The patent introduces a third metal layer above the second insulating layer, transitioning from a two-layer metal structure to a three-layer metal structure. This dimensional addition allows wiring to be distributed across three layers instead of two, reducing the horizontal space requirements and enabling a narrower GOA region while maintaining adequate spacing between wires to prevent short circuits.
Solution Approach 2:
The patent segments the wiring function across three separate metal layers, with each layer carrying specific connections. The first metal layer handles certain connections, the second metal layer handles others, and the third metal layer provides additional routing paths. This segmentation of wiring functions across multiple layers reduces congestion and allows for optimized spacing in each layer, thereby reducing the overall GOA region width.
2Area of stationary object
If the space between metal wires is reduced to achieve narrow-frame design, then the frame width can be reduced, but the risk of short circuit between metal wires increases
Solution Approach 1:
By adding the third metal layer in the vertical dimension, the patent provides additional routing paths that reduce the need for wires to be closely spaced in the same layer. Wires that would otherwise need to pass close to each other in two layers are now distributed across three layers, maintaining adequate spacing and reducing short circuit risk while achieving narrower frame width.
Solution Approach 2:
The patent introduces insulating layers (first and second insulating layers) as intermediaries between the metal layers. These insulating layers provide electrical isolation between adjacent metal wires in different layers, allowing wires to be positioned closer together horizontally while maintaining electrical safety. The insulating layers act as mediators that enable reduced spacing without increasing short circuit risk.
Data Source
AI summary
An array substrate and a display device having the array substrate are provided. The array substrate comprises a display region and a non-display region disposed at the periphery of the display region. The non-display region comprises a gate driver region (GOA region), which comprises a first patterned metal layer formed on a base substrate, a first insulating layer formed on the first patterned metal layer, a second patterned metal layer formed on the first insulating layer, a second insulating layer covering the second patterned metal layer, and a third patterned metal layer formed at a side of the second insulating layer away from the base substrate. The third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.