GOA Via Hole Transition Layer for Stable Electrical Connection

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Solution Overview

Problem

Traditional Gate driver on array (GOA) technology faces instability in the electrical connection between source-drain and gate metal electrodes due to chamfer openings formed during via hole etching, affecting the reliability of the gate drive circuit in TFT-LCDs.

Innovation Solution

The introduction of a transition layer with a higher etching rate than the active layer allows for the formation of an upward-opening angle at the via hole edges, enhancing the stability of the electrical connection between the source-drain and gate metal electrodes by forming a wider notch at the top and narrower notch at the bottom, ensuring a secure connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a via hole is formed by etching the gate insulating layer and active layer with the same masking process in the GOA region, then the number of masking processes is reduced to six, but the electrical connection between source-drain metal electrode and gate metal electrode becomes unstable

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidelectrical connection stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A transition layer is introduced as an intermediary between the active layer and the via hole etching process. This transition layer has a higher etching rate than the active layer, allowing it to be selectively removed to form an upward-opening angle at the via hole edge, which improves electrical connection stability while maintaining the streamlined six-mask manufacturing process

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the etching rate of the transition layer is made larger than the etching rate of the active layer, then an upward-opening angle is formed at the via hole edges improving connection stability, but the etching process becomes more complex

Engineering Contradiction:
Improveelectrical connection stabilityVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transition layer is applied locally only in the GOA region where via holes need to be formed, rather than uniformly across the entire substrate. This localized application allows for selective etching with different rates in different regions, achieving the upward-opening angle for improved connection stability without significantly complicating the overall etching process

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly improves the stability and reliability of the electrical connection between the source-drain and gate metal electrodes, enhancing the overall performance of the GOA region in TFT-LCDs.

Implementation Method 1

an etching rate of the transition layer is larger than the an etching rate of the active layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10204936B2Array substrate and method for manufacturing the same, display device
Publication Date: 2019.02.12 BOE TECHNOLOGY GROUP CO LTD
  • US10204936B2 patent drawing
  • US10204936B2 patent drawing
  • US10204936B2 patent drawing

AI summary

An array substrate includes a display region and a Gate driver On Array (GOA) region. In the GOA region, a gate metal electrode, a gate insulating layer, an active layer, a transition layer, and a source-drain metal electrode are formed in sequence from bottom to top, and a via hole is provided penetrating the transition layer, the active layer and the gate insulating layer, the source-drain metal electrode is electrically connected to the gate metal electrode through the via hole; and at an edge of the via hole, there is formed an angle opening upward at edges of the transition layer and the active layer. There are further disclosed a manufacturing method of the array substrate and a display device provided with the array substrate.