GPU-Based AIG Logic Rewriting for Lockless Parallel Acceleration
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Solution Overview
Problem
Existing CPU-based parallel logic rewriting algorithms fail to utilize intra-node parallelism effectively and suffer from low efficiency due to excessive use of locks, leading to reduced inter-node parallelism and increased communication overhead.
Innovation Solution
A GPU-based logic rewriting acceleration method that parallelizes sub-procedures such as cut enumeration and MFFC computation, employs a lockless replacement algorithm, and utilizes a node scheduler to group nodes with non-overlapping MFFCs, along with a hyper-node data structure to support concurrent operations without locks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU-based parallel logic rewriting algorithm uses locks to ensure thread exclusivity, then replacement step can be parallelized, but inter-node parallelism effectiveness is greatly reduced
Solution Approach 1:
The patent extracts the locking mechanism from the parallel replacement process and replaces it with a checkpoint-based validation approach. Each thread operates independently without locks, and correctness is ensured by validating against checkpoints rather than using mutual exclusion, thereby eliminating lock overhead and improving parallel efficiency
Solution Approach 2:
The patent substitutes the mechanical locking system with a software-based checkpoint validation system. Instead of using hardware or software locks to control access, the system uses validation against saved checkpoints to ensure correctness, replacing a contention-based mechanism with a validation-based mechanism
2Speed
If GPU-based parallel logic rewriting algorithm accelerates cut enumeration and evaluation steps, then node-level parallelism is improved, but communication overhead between CPU and GPU increases significantly
Solution Approach 1:
The patent merges the cut enumeration, evaluation, and replacement steps into a unified GPU-accelerated process. By combining these previously separate steps that required CPU-GPU communication into a single integrated workflow that runs entirely on the GPU, the patent eliminates multiple communication rounds and reduces overall communication overhead
Solution Approach 2:
The patent enables continuous processing by keeping all rewriting operations (cut enumeration, evaluation, and replacement) running continuously on the GPU without interruption for CPU communication. This continuous execution on the GPU accelerator eliminates the stop-start nature caused by frequent CPU-GPU data transfers
3Productivity
If CPU-based parallel algorithm uses inter-node parallelism with locks, then multiple threads can access different nodes simultaneously, but intra-node parallelism cannot be utilized
Solution Approach 1:
The patent segments the rewriting operations into independent fine-grained tasks that can be executed in parallel within each node. By dividing the work into smaller independent units (cut enumeration, evaluation, replacement) that don't require mutual exclusion, the system enables both inter-node and intra-node parallelism simultaneously
Solution Approach 2:
The patent adds another dimension to parallelism by enabling parallel execution both across nodes (inter-node) and within nodes (intra-node). The checkpoint-based validation approach allows fine-grained parallelism within nodes while maintaining correctness, creating a two-dimensional parallel execution model
Data Source
AI summary
A graphics processing unit (GPU)-based logic rewriting acceleration method comprising parallelizing sub-procedures of And-Inverter Graph (AIG)-based logic rewriting. A recursive sub-procedure of the AIG-based logic rewriting is redesigned to be non-recursive, to provide sufficient parallelism for a GPU. In order to parallelize a replacement step on the GPU, the present disclosure uses a lock to ensure mutually exclusive access, which inevitably damages scalability of inter-node parallelism. In order to fully utilize the inter-node parallelism on a large scale, the present disclosure proposes a work scheduler that adds nodes with non-overlapping maximum fan-out-free cones (MFFCs) to a group, such that nodes in an MFFC can be deleted simultaneously without a conflict. In order to simultaneously create and delete a same node, the present disclosure also proposes a GPU-friendly graphical data structure to support these concurrent operations.