GPU Floating-Point Units with Configurable Precision for Faster AI Training

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increasing size of datasets used to train artificial intelligence models leads to slow training times and high energy consumption, posing challenges in efficiently training and deploying AI models.

Innovation Solution

The implementation of a fully configurable floating-point format in graphics processing units (GPUs) allows for dynamic precision adjustments, optimizing memory usage and computation efficiency during training operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If standard floating-point formats are used for training AI models with large datasets, then computation accuracy is maintained, but training time increases and energy consumption rises

Engineering Contradiction:
Improvetraining speedVSAvoidtraining time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic precision configuration where the floating-point format parameters (exponent width, significand width, rounding mode) can be changed at runtime based on the specific computational requirements of different AI training operations. This allows the system to adaptively switch between high-precision and low-precision formats, optimizing training speed while maintaining necessary accuracy for each operation type.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the fundamental parameters of the floating-point representation by allowing configurable exponent and significand widths. By adjusting these parameters, the system can use narrower formats (reducing computation time and energy) when high precision is not critical, and wider formats when accuracy is paramount, thus resolving the contradiction between speed and accuracy.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If high precision floating-point formats are used, then computation accuracy is improved, but memory requirements and energy consumption increase

Engineering Contradiction:
Improvecomputation accuracyVSAvoidenergy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies different precision levels to different parts of the AI training process based on their specific requirements. Critical operations that demand high accuracy use wider floating-point formats, while less sensitive operations use narrower formats. This local differentiation of precision quality reduces overall energy consumption while maintaining necessary accuracy where required.

Inventive Principle:
Principle #3Local quality

3Device complexity

If fixed precision floating-point formats are used, then hardware implementation is simplified, but adaptability to different AI training requirements is reduced

Engineering Contradiction:
Improvehardware complexityVSAvoidformat configurability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent designs a universal floating-point unit that can handle multiple precision formats (different exponent and significand widths) and rounding modes within a single hardware structure. This multi-functional design allows the same hardware to adapt to various AI training requirements without requiring separate specialized units for each format, thus maintaining relatively simple hardware while achieving high versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250291547A1Fully configurable floating-point format
Publication Date: 2025.09.18 INTEL CORP
  • US20250291547A1 patent drawing
  • US20250291547A1 patent drawing
  • US20250291547A1 patent drawing

AI summary

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets comprising a graphics processing cluster including a plurality of processing resources. At least one processing resource of the plurality of processing resources includes a dynamic precision floating-point unit having floating-point circuitry configured to process input in a configurable floating-point format having a variable number of exponent and mantissa bits.