GPU Data Queuing via Banked Storage and Dynamic Selection

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Solution Overview

Problem

Graphics Processing Units (GPUs) face challenges in scaling queue structures to avoid latency and conflict issues, leading to wire routing congestion and increased power consumption, particularly in mobile devices where power management is critical.

Innovation Solution

A unified shading cluster is introduced, featuring a selection circuit and storage array with multiplex circuits to selectively couple data bits to data lines, allowing for efficient data routing and reformatting, thereby minimizing wire routing congestion and enabling scalable queue structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If queue structures are scaled to avoid latency and conflict issues, then reliability is improved, but wire routing congestion increases

Engineering Contradiction:
Improvequeue operation reliabilityVSAvoidwire routing congestion
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The queue structure is divided into multiple banks (e.g., first bank, second bank, third bank, fourth bank) that can operate independently. Each bank handles a portion of the data bits, allowing parallel operations and reducing conflicts. The segmentation enables the system to scale capacity without proportionally increasing wire routing complexity, as each bank has its own dedicated storage units and selection circuits.

Inventive Principle:
Principle #1Segmentation

2Productivity

If queue structures are scaled to avoid latency issues, then productivity is improved, but wire routing congestion increases

Engineering Contradiction:
Improvedata processing throughputVSAvoidwire routing congestion
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a bank dimension to organize storage units, transforming a flat scaling approach into a multi-dimensional structure. Data bits are distributed across multiple banks, each with its own storage units and selection circuits. This dimensional organization allows parallel data processing and reduces wire routing congestion by localizing connections within each bank while maintaining high throughput across the entire queue structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If more data lines are added to handle increased data throughput, then productivity is improved, but power consumption increases

Engineering Contradiction:
Improvedata throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The selection circuits dynamically route data bits to appropriate storage units based on current operation requirements. Instead of maintaining static connections for all possible data paths, the system activates only the necessary data lines and selection circuits for each operation. This dynamic routing reduces power consumption by minimizing active circuitry while maintaining the capability for high data throughput when needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10769746B2Data alignment and formatting for graphics processing unit
Publication Date: 2020.09.08 APPLE INC
  • US10769746B2 patent drawing
  • US10769746B2 patent drawing
  • US10769746B2 patent drawing

AI summary

A data queuing and format apparatus is disclosed. A first selection circuit may be configured to selectively couple a first subset of data to a first plurality of data lines dependent upon control information, and a second selection circuit may be configured to selectively couple a second subset of data to a second plurality of data lines dependent upon the control information. A storage array may include multiple storage units, and each storage unit may be configured to receive data from one or more data lines of either the first or second plurality of data lines dependent upon the control information.