GPU-Accelerated Mutation Testing for Simulation and Formal Verification
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Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in efficiently performing mutation testing and formal verification due to limitations in parallel processing capabilities and the need for specialized operations that are not adequately addressed by traditional fixed function computational units.
Innovation Solution
Utilizing a general-purpose graphics processing unit (GPGPU) with dedicated circuitry for efficiently processing commands and instructions, coupled with host processors to accelerate mutation testing and formal verification through parallel processing techniques such as pipelining and SIMT architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fixed function computational units are used in GPUs, then the architecture is simple and reliable, but the adaptability for specialized operations like mutation testing is insufficient
Solution Approach 1:
The patent implements programmable computational units within the GPU architecture that can be configured to perform different operations including mutation testing, formal verification, and traditional graphics processing. This multi-functionality allows a single hardware unit to adapt to various computational tasks through software control and configuration, resolving the contradiction between adaptability and complexity.
Solution Approach 2:
The computational units are designed with dynamic reconfigurability, allowing them to change their functional behavior based on the task at hand. The hardware can be dynamically programmed to perform mutation testing operations when needed, and revert to or switch between other operations, providing adaptability without permanently increasing structural complexity.
2Productivity
If parallel processing capabilities are increased for mutation testing, then the productivity improves, but the device complexity increases
Solution Approach 1:
The patent divides the mutation testing workload into multiple independent parallel threads that can be executed simultaneously across different GPU cores. Each thread handles a specific mutation testing task, and the results are aggregated. This segmentation enables high productivity through parallelism while keeping individual processing units relatively simple and manageable.
Solution Approach 2:
The patent combines mutation testing operations with the existing GPU parallel processing architecture, merging the verification tasks into the graphics processing pipeline. By integrating mutation testing into the established parallel framework rather than creating a separate system, the patent achieves high productivity while leveraging existing infrastructure to minimize additional complexity.
3Manufacturing precision
If specialized circuitry is added for mutation testing operations, then the manufacturing precision for verification tasks improves, but the ease of manufacture decreases
Solution Approach 1:
Rather than adding specialized circuitry for mutation testing, the patent uses the existing GPU computational units to perform verification tasks through programming. This approach maintains manufacturing simplicity while achieving high verification accuracy through software-controlled precise operations, avoiding the need for complex custom hardware fabrication.
Data Source
AI summary
An apparatus to facilitate accelerating mutation testing for simulation and formal verification is disclosed. The apparatus includes processing circuitry to define a set of mutations and a set of verification properties for an original design under test (DUT); utilize a conditional input bit to conditionally activate the set of mutations in the original DUT; generate a conditional DUT comprising the original DUT having the conditional input bit applied to the set of mutations; for each verification property, inspect a query associated with the verification property and the conditional DUT to determine whether the verification property has at least one mutation of the set of mutations that has a corresponding conditional input bit that is present; and run a verification sign-off tool that executes the verification properties that are determined to have the at least one mutation of the set of mutations with the corresponding conditional input bit that is present.