GPU Parallel Execution for Graphics and Machine Learning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current graphics processing units (GPUs) face limitations in efficiently processing graphics and machine-learning operations due to the need for optimized parallel processing techniques and architectures that maximize throughput in graphics pipelines.

Innovation Solution

A computing system is described that includes a graphics processing unit (GPU) communicatively coupled to host processor cores, utilizing a parallel processor architecture with multiple processing clusters and a scheduler to distribute work efficiently across the GPU, enabling simultaneous execution of graphics and machine-learning operations through optimized interconnects and memory management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional fixed function computational units are used in graphics processors, then specific graphics operations can be processed efficiently, but the processor cannot support a wider variety of operations for processing vertex and fragment data

Engineering Contradiction:
Improvevariety of operationsVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies universality by making portions of graphics processors programmable, enabling a single processor to support both traditional graphics operations and a wider variety of vertex and fragment data processing operations through programmable execution units that can be configured for different tasks

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If pipelining is implemented to process graphics data in parallel, then processing throughput is increased, but the complexity of coordinating multiple threads executing synchronously increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidcoordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the graphics processing task into multiple independent threads that can execute in parallel through pipelining, with each thread handling specific portions of the processing workload while maintaining synchronization through the SIMT architecture

Inventive Principle:
Principle #1Segmentation

3Productivity

If single instruction multiple thread (SIMT) architecture is used to maximize parallel processing, then processing efficiency is increased, but the ability to handle divergent execution paths reduces

Engineering Contradiction:
Improveparallel processing efficiencyVSAvoiddivergent execution capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by implementing a flexible thread execution model where threads can be dynamically scheduled and coordinated, allowing the system to adapt between synchronous parallel execution for maximum efficiency and more flexible execution patterns when needed for divergent paths

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12100103B2Converting barycentric planes to attribute planes
Publication Date: 2024.09.24 INTEL CORP
  • US12100103B2 patent drawing
  • US12100103B2 patent drawing
  • US12100103B2 patent drawing

AI summary

Methods, systems and apparatuses provide for graphics processor technology that generates attribute plane coefficients based on barycentric coefficients, wherein the attribute plane coefficients are generated on a per polygon basis, and interpolates one or more pixel attributes based on the attribute plane coefficients. In one example, the technology excludes the barycentric coefficients from one or more per pixel operations.