Processor Architectures/Configuration TRIZ Cases
- Distributed Deep Neural Network Training via Subnetwork Segmentation
Segmenting deep neural networks into subnetworks reduces network delay and data transmission time during distributed training.
- Pre-compiled Shader Chunk Assembly for Avionics Certification
Concatenating pre-compiled shader chunks emulates fixed-function graphics pipelines on programmable hardware.
- 3D Shape Data Processing with Adaptive Voxel Segmentation
Adaptive voxel segmentation extracts unit shapes to configure flat faces, resolving surface inconsistencies caused by varying voxel sizes.
- Ray Tracing Acceleration Structure Morton Code Bounding Box
Morton code arranges primitives into bounding boxes, reducing computational complexity and memory bandwidth in ray tracing.
- Rasterization Partial Span Identification for MSAA Block Reduction
Extracts partial spans from pixel subsets to lower power consumption and chip area during multi-sampling anti-aliasing.
- Human Detection Accuracy in Variable Crowd Density
A dual-unit image processing system combines trained models with pattern matching for human detection.
- Graphics Processor Ray Tracing Bounding Volume Hierarchy Optimization
A graphics processor omits intersection tests against bounding volume primitives using a hierarchical acceleration structure.
- Shader Sequence Snapshot Error Localization
Intermediate snapshot comparison isolates error-causing shaders in complex sequences, reducing debugging time and resource consumption.
- Dynamic Asynchronous Time Warping for GPU Rendering Efficiency
A rendering method adjusts asynchronous time warping timing based on frame completion status to optimize GPU resource usage.
- Flexible Compression Jumper Connector for Motherboard Graphics Board Transition
A flexible compression jumper connector links motherboard and graphics board arrays via compressible pads.
- Agentless System Error Management via Graphics Comparison
A management controller compares actual output graphics against intended content to detect and remove extraneous visual elements from the display.
- Dynamic Performance Adjustment for Split XR Applications
Machine learning models predict frame processing times to adjust rendering pipeline parameters, reducing motion-to-render-to-photon latencies and frame repeats.
- GPU Parallel Execution for Graphics and Machine Learning
A graphics processing unit executes tasks in parallel to maximize throughput across multiple processing clusters.
- Adaptive Sub-patches System for Graphics Processing Efficiency
Adaptive sub-patches system subdivides patches into variable tessellation regions to optimize rendering granularity.
- Graphics Processor Simulation Using Programmable Circuitry
A native graphics processor executes executable program instructions to replicate fixed function operations of a target device.
- Tile Rendering Cost Estimation for Load Balancing
Cost estimation model predicts tile processing time to split expensive tiles, resolving back-end pipeline load imbalance.
- CPU Image Processing via Optimized Computation Units
Optimized computation units leverage CPU instruction sets to process medical images, reducing GPU dependency and hardware costs.
- Layered Surface Property Generation for Rendering Efficiency
A layered surface property generation system computes and caches intermediate image layers to reuse data across frames.
- Graphics Processing Concurrency via Task Completion Tracking
Tracking rendering task completion status allows overlapping job execution to resolve core utilization bottlenecks while enforcing data dependencies.
- Graphics Pipeline Discarding Non-Contributing Shaded Fragments
Discards non-contributing shaded fragments in the graphics pipeline to reduce power consumption.
- Shader Warp Packer Unit for Small Primitive Processing
A shader warp packer unit packs non-overlapping partially covered quads into a single packed quad for efficient processing.