Tile-Based GPU Tessellation Control for Embedded Power
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Solution Overview
Problem
Graphic processing units (GPUs) in embedded devices, such as smartphones and tablets, face challenges in providing high graphic processing performance due to low processing capability and high power consumption, making it difficult to deliver the same performance as workstations, despite increasing demand for graphics-intensive applications.
Innovation Solution
A tile-based graphics pipeline method is implemented, which includes a binning pipeline that generates an output patch, determines the number of tiles it includes, decides on tessellation, and bins a tile list based on tessellation, and performs a rendering pipeline per tile, optimizing performance by skipping tessellation when the output patch is in one tile and performing tessellation when it spans multiple tiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If tessellation is performed on all output patches, then rendering quality is improved, but processing time and power consumption increase
Solution Approach 1:
The patent changes the parameter of tessellation application by introducing a conditional parameter: tessellation is applied only when the output patch spans multiple tiles (number of tiles > 1). This parameter-based selection resolves the contradiction by maintaining high rendering quality where needed (at tile boundaries) while avoiding unnecessary tessellation processing in single-tile patches, thus reducing processing time and power consumption.
2Manufacturing precision
If tessellation is performed on all output patches, then rendering quality is improved, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by making tessellation execution conditional on the number of tiles containing the output patch. When the patch is contained within a single tile, tessellation is skipped, directly reducing power consumption. When the patch spans multiple tiles, tessellation is performed to maintain rendering quality at tile boundaries, thus resolving the power consumption vs. quality trade-off.
3Use of energy by moving object
If conditional tessellation is performed only when output patch spans multiple tiles, then power consumption is reduced, but rendering quality may be compromised
Solution Approach 1:
The patent applies local quality by differentiating tessellation requirements based on spatial location. Patches at tile boundaries (spanning multiple tiles) receive full tessellation processing to maintain high rendering quality, while patches entirely within single tiles use simplified rendering. This localized approach ensures quality is maintained where it matters most (tile boundaries) while reducing overall power consumption.
Data Source
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AI summary
Computing apparatus and methods are provided for performing a tile-based graphics pipeline. The graphics pipeline includes a binning pipeline configured to generate a tile list of objects indicating which tile vertices, primitives, or patches the objects belong to; and a rendering pipeline configured to render an object, per tile, based on the tile list generated in the binning pipeline. Each of the binning pipeline and the rendering pipeline is configured to implement a tessellation pipeline. The graphics pipeline may be configured to operate in an efficiency mode to defer or lower tessellation by performing tessellation in one of the binning and rendering pipelines or by setting a new lower tessellation factor.