Processor Architectures/Configuration TRIZ Cases
- Out-of-band Interconnect Control for Cloud Domain Isolation
A hypervisor manages specialized interconnects between peripheral processors to enable secure data transfer across virtual machine domains.
- GPU Path Rendering Tile Splitting and Winding Number Allocation
A rendering apparatus splits frames into tiles to allocate path information for targeted winding number calculations.
- Variable Rate Shading Gradient Post-Processing for GPU Image Quality
Gradient interpolation of corner pixels maintains image quality while reducing computational load for large variable rate shading kernels.
- Geospatial Dataset Distribution via Low-Discrepancy Sequences
Low-discrepancy sequences distribute geospatial data objects across computing units to resolve load imbalance in large-scale seismic surveys.
- GPU Conditional Rendering via Shadow Indirect Buffer
Segmenting instructions into primary and shadow buffers allows skipping invisible primitives while maintaining scene integrity.
- CPU-GPU Collaborative Rendering for Virtual Scene Efficiency
A collaborative rendering method distributes computing tasks between the central processing unit and graphics processing unit to optimize resource usage.
- Tile-Based GPU Tessellation Control for Embedded Power
Conditional tessellation skips processing for single-tile patches, reducing power consumption while maintaining rendering quality at tile boundaries.
- V-PCC 3D Bounding Box Scale Parameter for AR Point Cloud Integration
A V-PCC bitstream carries a 3D bounding box scale parameter to transform coded sample positions from local coordinates into real-world dimensions.
- Position-Only Shading Pipeline Reduces Memory Traffic
A position-only shading pipeline sorts triangles by depth to optimize rendering bins.
- Plugin Selection via Connection Library for Image Processing
A connection library selects image processing plugins by name and parameters.
- GPU Admission Control for Network Packet Processing
A network device uses a GPU admission control module to assess available resources and schedule applications accordingly.
- Tiling Circuit Motion Detection for Graphics Rendering
A tiling circuit divides input frames into tiles and checks their motion state to determine processing requirements.
- Multi-SoC Graphics Processing via External Circuit Segmentation
A graphics processing device uses an external circuit to segment data between two SoCs for parallel computation.
- Parallel 3D Acceleration Structure Construction in GPUs
Binary radix trees construct internal nodes alongside ancestors, resolving sequential bottlenecks and scaling performance linearly with core count.
- 3D Map Feature Rendering via GPU Sample Point Elevation
A client device selects a sample point on a map feature to determine top surface elevation for 3D rendering.
- AI Planning Problem Translation System for Domain Experts
A translation system converts graphical domain knowledge representations into AI planning problems.
- Parallel Optical Image Computing Architecture
Massive parallel digital image computer architecture converts visual data into binary form for processing across multiple nodes.
- Depth Data Preservation in Image Editing via Calibration Matrix Updates
A depth-enhanced image editing system updates calibration matrices to align edited images with original depth data.