Multi-SoC Graphics Processing via External Circuit Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current systems-on-a-chip (SoCs) with varying arithmetic capabilities are not cost-effective for use in both low-end and high-end electronic products, as high-end SoCs are costly to manufacture and integrate, and existing multi-core and multi-cluster technologies do not effectively leverage cooperation between multiple SoCs for enhanced graphics processing performance.

Innovation Solution

A graphics processing device comprising multiple SoCs that cooperate through an external circuit to divide and process data, with each SoC handling a portion of the image data to achieve higher processing performance than either SoC could alone, enabling the use of low-end SoCs in low-end products and combining them for high-end products.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an SoC with high arithmetic capability is used to achieve high graphics processing performance, then the processing performance is improved, but the manufacturing cost and device complexity increase

Engineering Contradiction:
Improvegraphics processing performanceVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the graphics processing task into multiple segments, with each low-end SoC handling a specific portion of the data processing. The first SoC processes a first input part and generates first output data, while the second SoC processes a second input part and generates second output data. This segmentation allows the system to achieve high processing performance through multiple simpler units rather than one complex high-end SoC.

Inventive Principle:
Principle #1Segmentation

2Productivity

If an SoC with high arithmetic capability is used to achieve high graphics processing performance, then the processing performance is improved, but the manufacturing cost increases

Engineering Contradiction:
Improvegraphics processing performanceVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent uses multiple copies of the same low-end SoC design rather than a single high-end SoC. Each SoC is identical in structure and capability, processing a specific portion of the input data. This copying approach reduces manufacturing costs by using standardized, mass-producible low-end SoC designs instead of expensive custom high-end SoCs.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If multiple SoCs with different arithmetic capabilities are used to match different product segments, then the adaptability is improved, but the total research, development, and manufacturing cost increases

Engineering Contradiction:
ImproveadaptabilityVSAvoidtotal R&D and manufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent employs multiple SoCs with the same arithmetic capability and identical structure, where each SoC can independently process a portion of the input data. This universal design allows the same SoC model to be used across different product segments by simply varying the number of SoCs configured, rather than developing different SoC designs for different product tiers. The system achieves adaptability through configurability rather than hardware differentiation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11809337B2Graphics processing device
Publication Date: 2023.11.07 REALTEK SEMICON CORP
  • US11809337B2 patent drawing
  • US11809337B2 patent drawing
  • US11809337B2 patent drawing

AI summary

Disclosed is a graphics processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first graphics processing unit (GPU) dividing to-be-processed data into a first input part and a second input part, and processing the first output part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit and outputting the second output data to the main SoC via the external circuit; and a second GPU receiving the second input part from the second transceiver circuit and processing this part to provide the second output data for the second transceiver.