GPU Workgroup Rasterization for Pixel-Tile Cache Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The limited size of the level 2 (L2) cache in graphics processing units (GPUs) leads to partial eviction of cachelines, causing performance degradation due to slow data transfer and inefficient bandwidth usage when workgroups are misaligned with pixel tiles, preventing effective compression and coalescing of requests.
Innovation Solution
Implementing tiled workgroup rasterization with a snake walking order to align workgroups with pixel tiles, ensuring adjacent fibers access consecutive addresses and optimize L2 cache usage, thereby reducing partial eviction and improving coalescing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If workgroups are processed in traditional rasterization order, then processing simplicity is maintained, but L2 cache utilization deteriorates due to misalignment with pixel tiles causing partial eviction
Solution Approach 1:
The patent dynamically adjusts the rasterization order based on workgroup alignment with pixel tiles. When misalignment is detected, the system switches to a converted rasterization order that aligns workgroups with pixel tile boundaries, optimizing cache utilization. This dynamic adaptation resolves the contradiction by maintaining processing efficiency while improving bandwidth usage.
Solution Approach 2:
The patent changes the rasterization parameter (processing order) from traditional row-major to a converted order that aligns with pixel tile boundaries. This parameter change ensures workgroups are processed in an order that maximizes L2 cache utilization and minimizes partial eviction, thereby improving GPU performance while reducing bandwidth waste.
2Productivity
If L2 cache size is increased to reduce partial eviction, then cache utilization improves, but device complexity and cost increase
Solution Approach 1:
The patent performs preliminary alignment of workgroups with pixel tiles before processing by converting the rasterization order. This preliminary action ensures that when data is accessed during processing, it is already optimally positioned in the L2 cache, reducing partial eviction without requiring an increase in cache size. This resolves the contradiction by achieving better cache utilization through smart organization rather than brute-force expansion.
3Productivity
If traditional rasterization order is used, then implementation simplicity is maintained, but request coalescing efficiency deteriorates due to misaligned workgroup access patterns
Solution Approach 1:
The patent segments the image processing into pixel tiles, each aligned with workgroup boundaries. By dividing the processing space into tile segments that match workgroup dimensions, the system enables efficient request coalescing within each tile while maintaining overall processing efficiency. This segmentation approach resolves the contradiction by organizing data access patterns to naturally align with hardware boundaries.
Data Source
AI summary
The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.