Graded Doping Semiconductor Device for Low On-Resistance
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Solution Overview
Problem
Current semiconductor devices, particularly junction field effect transistors (JFETs), face challenges in reducing on-resistance and improving current density, which are crucial for minimizing power loss and handling inverse directional high voltages effectively.
Innovation Solution
The semiconductor device incorporates a specific layer structure with sequentially disposed n-type layers and a p-type region, including a trench and gate electrode, where the ion doping concentration gradient forms an acceleration electric field in the channel region, reducing on-resistance and enhancing current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional JFET structure is used, then manufacturing process is simple, but on-resistance is high and current density is low
Solution Approach 1:
The patent applies parameter changes by introducing a graded doping concentration structure in the second n-type layer, where the doping concentration decreases from bottom to top (first concentration layer > second concentration layer > third concentration layer > fourth concentration layer). This gradual parameter change creates an acceleration electric field that improves carrier drift velocity, thereby reducing on-resistance and increasing current density while maintaining the JFET manufacturing simplicity.
Solution Approach 2:
The patent applies local quality by creating different doping concentration regions within the second n-type layer. Each concentration layer (first, second, third, fourth) has a specific doping level tailored to its position, with the highest concentration at the bottom and lowest at the top. This localized variation in doping quality optimizes the electric field distribution specifically in the channel region, improving device performance without complicating the overall manufacturing process.
2Reliability
If higher doping concentration is used, then on-resistance decreases, but breakdown voltage decreases
Solution Approach 1:
The patent resolves this contradiction by implementing a graded doping concentration profile instead of a uniform high doping level. The doping concentration gradually decreases from the first concentration layer (highest) to the fourth concentration layer (lowest), creating an acceleration electric field that reduces on-resistance. Simultaneously, the lower doping concentrations in the upper layers maintain the depletion layer characteristics necessary for high breakdown voltage, thus achieving both low on-resistance and high breakdown voltage.
Solution Approach 2:
The patent applies dynamics by creating a dynamic electric field distribution through the graded doping structure. The varying doping concentrations generate an acceleration electric field that dynamically adapts to the carrier flow, providing strong field enhancement in regions where it is needed (near the source) while maintaining appropriate field levels elsewhere to ensure high breakdown voltage. This dynamic field distribution optimizes both on-resistance and breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases on-resistance by 18% and increases current density by 15%, thereby reducing the electrically conductive area, improving yield, and lowering overall costs.
Implementation Method 1
the ion doping concentration gradient forms an acceleration electric field in the channel region
Implementation Method 2
The ion doping concentration of the second concentration layer may be lower than the ion doping concentration of the first concentration layer, an ion doping concentration of the third concentration layer may be lower than the ion doping concentration of the second concentration layer, and an ion doping concentration of the fourth concentration layer may be lower than the ion doping concentration of the third concentration layer
Data Source
AI summary
A semiconductor device is provide. The device includes a first n− type of layer, a second n− type of layer, and an n+ type of region sequentially disposed on a first surface of a substrate. A trench is disposed on a side surface of the second n− type of layer, a p type of region is disposed between the second n− type of layer and the trench, and a gate electrode is disposed on a bottom surface of the trench. A source electrode is disposed on the n+ type of region and a drain electrode is disposed on a second surface of the substrate. The second n− type of layer includes a first concentration layer, a second concentration layer, a third concentration layer, and a fourth concentration layer sequentially disposed on the first n− type of layer.