Graded SiC-GeC Insulator Stack for Multifunctional Memory
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Solution Overview
Problem
Conventional DRAM and flash memory technologies face issues with high power consumption, frequent refreshing requirements, scalability problems, and incompatibility due to different cell designs and fabrication techniques, leading to a need for low power, scalable, and multifunctional memory cells.
Innovation Solution
The development of an integrated, multifunctional memory cell transistor with a graded composition gate insulator stack, featuring a substrate with implanted source and drain regions, a tunnel dielectric made of silicon carbide and germanium carbide, a charge blocking layer with embedded nano-crystals, and a gate structure that enables simultaneous DRAM and non-volatile memory functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM cells are used with stacked capacitors, then storage capacity is enhanced, but power consumption increases due to frequent refreshing requirements
Solution Approach 1:
The patent merges DRAM and flash memory functionalities into a single memory cell structure. The memory cell includes a floating gate for non-volatile storage and a depletion region capacitor for volatile storage, allowing both DRAM and flash operations in one device, thereby reducing the need for separate memory devices and their associated power consumption
Solution Approach 2:
The memory cell is designed to perform multiple functions: it can operate as a volatile DRAM cell for fast access, as a non-volatile flash cell for data retention, and support both read and write operations. This multi-functionality eliminates the need for separate DRAM and flash memory devices, reducing overall system power consumption
2Duration of action of stationary object
If floating gate flash memory is used for non-volatile storage, then data retention is improved, but power consumption increases due to high voltage requirements for programming and erase operations
Solution Approach 1:
The patent changes the electrical parameters dynamically by using a single supply voltage that can be adjusted between 0V and Vdd. By controlling the gate voltage and depletion region, the device can perform programming and erase operations without requiring the high voltages (typically 12V or higher) needed by conventional flash memory, thereby reducing power consumption while maintaining data retention
3Ease of manufacture
If DRAM and flash memory are produced on different silicon substrates, then manufacturing cost is minimized and product yield is maximized, but device complexity and integration difficulty increase
Solution Approach 1:
The patent combines DRAM and flash memory fabrication processes into a single integrated flow. Both memory types are formed on the same silicon substrate using compatible process steps, eliminating the need for separate manufacturing lines and reducing overall device complexity while maintaining manufacturing efficiency
4Area of moving object
If feature size is scaled down progressively, then device density is improved, but fundamental leakage issues such as short-channel effects and gate dielectric leakage worsen
Solution Approach 1:
The patent uses a composite gate dielectric structure consisting of multiple layers including oxide and nitride layers. This composite structure provides better electrical isolation and reduces gate leakage currents even as device dimensions are scaled down, thereby maintaining reliability while improving device density
Solution Approach 2:
The patent implements a depletion region capacitor structure where the depletion region is localized beneath the gate. This localized depletion region acts as an additional barrier against charge leakage, addressing the short-channel effects and gate dielectric leakage issues that arise with scaled-down feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides improved charge retention and faster write/erase times while reducing power consumption and fabrication costs, enabling the integration of multiple memory technologies on a single silicon substrate with adjustable volatility levels.
Implementation Method 1
The tunnel dielectric is formed from a graded composition of silicon carbide and germanium carbide
Implementation Method 2
The charge blocking layer has an imbedded charge trapping layer comprised of nano-crystals
Data Source
AI summary
A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of nano-crystals is formed in the charge blocking layer. In one embodiment, the charge blocking layer is comprised of germanium carbide and the nano-crystals are germanium. The thickness and/or composition of the tunnel insulator determines the functionality of the memory cell such as the volatility level and speed. A gate is formed over the charge blocking layer.