Gradient Doped Channel for 3D Memory Stacking
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Solution Overview
Problem
The challenge in manufacturing three-dimensional (3D) stacked semiconductor memory devices is the formation of channel structures with controlled electrical performance, as high aspect ratios and inconsistent widths lead to profile deformation and electrical property drift in the vertical stacking of transistors.
Innovation Solution
The method involves forming a channel structure in a film stack with alternating dielectric and conductive layers on a substrate, where the channel layer has a gradient dopant concentration and the protective blocking layer has a non-uniform thickness along the vertical stacking, ensuring consistent electrical performance by compensating for the channel structure's slope and width variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high aspect ratio channel structures are formed in 3D stacked memory devices, then device density and integration are improved, but profile deformation and tapering occur leading to inconsistent channel width
Solution Approach 1:
The patent applies local quality by introducing a protective blocking layer with non-uniform thickness distributed along the channel structure. The layer has greater thickness at regions where the channel width is smaller (typically the base or top depending on taper direction) and reduced thickness where the channel is wider, thereby locally compensating for tapering effects and maintaining consistent electrical characteristics throughout the vertical stack.
2Reliability
If repeatedly alternating layers are used in the film stack to improve device performance, then memory device performance is enhanced, but the channel structures develop high aspect ratios causing threshold voltage drift
Solution Approach 1:
The patent applies parameter changes by modifying the physical parameters of the protective blocking layer, specifically its thickness distribution along the vertical channel structure. By controlling the layer thickness to be non-uniform (thicker at narrow regions, thinner at wide regions), the electrical parameters such as threshold voltage are stabilized throughout the channel, compensating for the effects of high aspect ratio and maintaining consistent device performance.
3Ease of manufacture
If conventional etching processes are used to form trenches in the film stack, then channel structures are created, but profile deformation occurs reducing manufacturing precision
Solution Approach 1:
The patent applies the taking out principle by extracting or removing material to form the protective blocking layer with controlled non-uniform thickness. This layer is selectively formed or deposited and then potentially selectively removed or modified in specific regions to achieve the desired thickness profile that compensates for etching-induced tapering, thereby improving the final channel structure geometry without fundamentally changing the etching process itself.
Data Source
AI summary
The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.