Gradient Doped FinFET Recesses Reduce Channel Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in implementing FinFET device fabrication processes, particularly in advanced process nodes, where reducing channel and parasitic resistances is crucial to prevent latch-up issues and improve performance, especially when using metal gate electrodes.
Innovation Solution
The formation of gradient doped regions in the fin structures, specifically along the bottom surface of recesses in the FinFET devices, helps reduce channel and parasitic resistances by strategically implanting dopants to create a controlled dopant gradient profile, which is achieved through a method involving the formation of dummy gate structures, gate spacers, and subsequent doping processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gradient doped regions are formed in recessed fins, then channel resistance and parasitic resistance are reduced, but device fabrication complexity increases
Solution Approach 1:
The method performs preliminary actions by forming dummy gate structures and gate spacers before the actual doping process. These preliminary structures serve as masks and guides for subsequent dopant implantation, enabling precise gradient doping profiles to be achieved in the recessed fin regions without requiring complex direct doping techniques
Solution Approach 2:
The invention applies local quality by creating gradient doped regions with varying dopant concentrations at different locations within the recessed fins. The dopant concentration is strategically varied from the bottom to the top of the recessed regions, providing locally optimized electrical properties that reduce channel and parasitic resistance while maintaining overall device performance
2Reliability
If gradient doped regions are formed in recessed fins, then parasitic resistance is reduced, but manufacturing process steps increase
Solution Approach 1:
The method merges multiple functions into unified process steps. The dummy gate structures and gate spacers serve dual purposes: they act as protective masks during doping while also defining the precise geometry of the gradient doped regions. This consolidation reduces the need for separate masking and alignment steps, improving manufacturing throughput despite the added doping complexity
3Reliability
If dopant gradient profile is implemented, then carrier mobility is improved, but doping process precision requirements increase
Solution Approach 1:
The dummy gate structures and gate spacers serve as intermediary elements that mediate the doping process. These intermediary structures act as physical masks that automatically define the dopant concentration profile through their geometry, eliminating the need for complex real-time concentration control during implantation. The intermediary structures translate simple geometric parameters into precise dopant distribution patterns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers channel resistance and parasitic resistance, reducing the likelihood of latch-up issues and enhancing the performance of FinFET devices by improving carrier mobility and drive current, while avoiding the need to increase isolation region sizes.
Implementation Method 1
A gradient doped region is formed in the fin with a p-type dopant
Data Source
AI summary
An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions.