Graphene Interconnect Structure for Lower Capacitance Coupling
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Solution Overview
Problem
As semiconductor device dimensions decrease, the challenge of reducing capacitance coupling and improving semiconductor devices with reduced capacitance becomes essential, as existing technologies face limitations in defining structures photo-lithographically, leading to increased capacitance and reliability issues.
Innovation Solution
The implementation of a method involving the formation of graphene layers on conductive features within semiconductor devices to prevent catalyst layer formation and selectively grow dielectric materials, which creates a height difference that prevents conductive features from forming between neighboring conductive layers, thereby reducing line-to-line leakage and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are reduced to increase density, then device functionality and performance are improved, but capacitance coupling between adjacent structures increases
Solution Approach 1:
A dielectric material is introduced as an intermediary substance between adjacent conductive features. This dielectric layer acts as a mediator that reduces the electrical field interaction between neighboring conductors, thereby minimizing capacitance coupling while allowing the conductive features to remain in close proximity for high-density device design.
Solution Approach 2:
The patent applies different materials with specific properties to different regions of the device structure. Low-k dielectric materials are selectively placed in regions where capacitance reduction is most critical, such as between parallel interconnect lines, while other regions may use different dielectric or conductor materials optimized for their specific functional requirements.
2Length of moving object
If photo-lithographic definition capabilities are exceeded to create smaller structures, then device dimensions are reduced, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent replaces traditional photo-lithographic patterning with direct lithography or self-aligned formation methods. Conductive features are formed by directly depositing and patterning conductive materials without relying on photo-resist based approaches, thereby achieving sub-photo-lithographic dimensions with improved precision and reduced manufacturing variability.
Solution Approach 2:
The patent employs preliminary formation of sacrificial structures or templates that guide the subsequent formation of conductive features. These preliminary structures are formed with precise dimensions and positions, and they serve as alignment references or physical guides during the formation of the final conductive patterns, ensuring high manufacturing precision even at reduced dimensions.
3Productivity
If conductive features are placed closer together to increase density, then device functionality is improved, but line-to-line leakage increases
Solution Approach 1:
A dielectric material is introduced as an intermediary substance between adjacent conductive features. This dielectric layer acts as a mediator that reduces the electrical field interaction between neighboring conductors, thereby minimizing capacitance coupling while allowing the conductive features to remain in close proximity for high-density device design.
Solution Approach 2:
The patent addresses line-to-line leakage by transitioning from a two-dimensional planar separation approach to a three-dimensional solution. Instead of merely increasing horizontal spacing between conductors, the patent introduces vertical separation through multi-layer dielectric structures and varying conductor heights, effectively utilizing the vertical dimension to reduce parasitic coupling while maintaining high horizontal density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced sheet resistance, minimized line-to-line leakage, and lower capacitance, enhancing the reliability and performance of semiconductor devices by self-aligning conductive features and reducing capacitive coupling.
Implementation Method 1
The one or more graphene layers prevent a catalyst layer from forming thereon
Implementation Method 2
A dielectric material is selectively formed on the catalyst layer
Data Source
AI summary
An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.