Graphene-Coated Interconnects for Heat-Resistant Semiconductor Packaging

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Solution Overview

Problem

Semiconductor devices face challenges with heat dissipation and internal stress due to high processing demands and shrinking sizes, with existing vertical interconnects being inadequate in terms of heat dissipation and hardness.

Innovation Solution

The use of graphene-coated interconnects, which provide enhanced electrical conductivity, thermal conductivity, and hardness, along with improved solderability, to form semiconductor packages that can withstand high temperatures and internal stresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional vertical interconnects are used in semiconductor packages, then the device structure is simple and manufacturing is easier, but heat dissipation capability is insufficient and mechanical strength is inadequate under high temperature and stress conditions

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidinterconnect structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent applies composite materials by coating conventional interconnect structures with graphene material. This creates a composite interconnect system where the base interconnect provides structural support and the graphene coating provides enhanced thermal conductivity and mechanical strength. The composite structure resolves the contradiction by improving heat dissipation capability without fundamentally changing the overall interconnect architecture, thus maintaining manufacturing feasibility while achieving superior thermal performance.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the thermal and mechanical parameters of the interconnect structure by applying a graphene coating. This coating fundamentally alters the thermal conductivity parameter and mechanical strength parameter of the interconnect without changing its basic geometric parameters or electrical function. The parameter change approach allows the interconnect to withstand higher temperatures and stresses while maintaining the same structural form factor.

Inventive Principle:
Principle #35Parameter changes

2Strength

If conventional vertical interconnects are used, then manufacturing processes are simpler, but the interconnects cannot withstand high internal stresses from vibration and physical shock

Engineering Contradiction:
Improvemechanical strength and hardnessVSAvoidmanufacturing process complexity
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The graphene-coated interconnect structure creates a composite material system where the underlying interconnect provides structural framework and the graphene layer provides enhanced mechanical strength and hardness. This composite approach allows the interconnect to withstand high internal stresses from vibration and physical shock while using standard interconnect manufacturing processes for the base structure, thus resolving the contradiction between strength improvement and manufacturing simplicity.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The graphene coating acts as an intermediary layer between the interconnect structure and the harsh environmental conditions (vibration, shock, high temperature). This intermediary layer protects the base interconnect material from direct exposure to stress and thermal degradation, thereby enhancing mechanical strength without requiring fundamental changes to the manufacturing process for the underlying structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If graphene-coated interconnects are used, then heat dissipation and mechanical strength are improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveperformance under high temperature and stressVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the surface properties of existing interconnects through graphene coating rather than redesigning the entire interconnect system. This approach changes the thermal and mechanical parameters of the interconnect while maintaining compatibility with conventional interconnect manufacturing processes. The coating can be applied as an additional step without fundamentally altering the core manufacturing methodology, thus improving reliability while limiting the increase in manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The graphene-coated interconnects improve heat dissipation and mechanical strength, enabling higher performance in high-bandwidth applications while reducing manufacturing costs.

Implementation Method 1

The graphene coating 124 has a low moisture permeability and a high thermal conductivity of 4000-5000 W/mK

Methodology Applied
Scientific EffectThermal conductivity: Conduction (thermal)

Implementation Method 2

Graphene-coated interconnects 130 with graphene coating 124 have 100-times the electrical conductivity of Cu balls alone

Methodology Applied
Scientific EffectElectrical conductivity: Conduction (electrical)

Implementation Method 3

Graphene coating 124 also reduces or eliminates oxidation of core 120

Methodology Applied
Scientific EffectOxidation resistance: Oxidation

Data Source

PatentUS12581974B2Semiconductor device and method of making a semiconductor package with graphene-coated interconnects
Publication Date: 2026.03.17 STATS CHIPPAC LTD
  • US12581974B2 patent drawing
  • US12581974B2 patent drawing
  • US12581974B2 patent drawing

AI summary

A semiconductor device includes a first substrate and a second substrate. A graphene-coated interconnect is disposed between the first substrate and second substrate. A semiconductor die is disposed between the first substrate and second substrate. The first substrate is electrically coupled to the second substrate through the graphene-coated interconnect. An encapsulant is deposited between the first substrate and second substrate.