Graphene Oxide Memory Cell for High-Density Storage
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in miniaturization and integration due to limitations in reducing transistor size below 7 nm, and the three-dimensional stacked structure of NAND flash memory, which leads to interference issues between adjacent cells in orthogonal bar cell arrays, complicating the manufacturing process and reducing integration density.
Innovation Solution
A nonvolatile memory device with multi-level resistance and capacitance characteristics is developed, utilizing a substrate, dielectric layer with self-rectifying properties, and an active layer comprising a graphene oxide complex, which changes resistance and capacitance values based on applied voltage, eliminating the need for additional selection devices and simplifying the structure and process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional stacked structure is used to increase memory capacity, then integration density is improved, but interference between adjacent cells occurs causing reading errors
Solution Approach 1:
The patent extracts the rectifying function from separate selection devices (diodes or transistors) and integrates it into the unit device structure itself through the graphene oxide complex layer, eliminating the need for additional rectifying elements that would increase cell size and complexity
Solution Approach 2:
The patent uses a composite material structure consisting of a graphene oxide complex layer combined with a resistance variable layer, creating a unit device that inherently possesses both resistance switching and self-rectifying characteristics, thereby preventing interference currents while maintaining high integration density
2Reliability
If additional selection devices are added to each cell to prevent interference, then reading operation accuracy is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the rectifying function with the resistance switching function in a single unit device structure. The graphene oxide complex layer provides self-rectifying characteristics that enable selective reading of each cell without requiring separate selection devices, thereby simplifying the overall device architecture and reducing manufacturing complexity
Solution Approach 2:
The unit device structure is designed to perform multiple functions simultaneously: resistance switching for data storage and self-rectifying for selective reading. This multi-functional design eliminates the need for additional dedicated selection devices, reducing device complexity while maintaining reading accuracy
3Length of moving object
If transistor size is reduced below 7 nm to improve integration, then miniaturization is achieved, but physical and technical limitations prevent further reduction
Solution Approach 1:
The patent replaces the conventional transistor-based resistance switching mechanism with a novel mechanism based on a graphene oxide complex layer combined with a resistance variable layer. This substitution enables continued miniaturization beyond the 7 nm limit by using a different physical mechanism that does not suffer from the same scaling limitations
Solution Approach 2:
The patent employs a composite material system consisting of graphene oxide complex and resistance variable layer that enables miniaturization at dimensions below 7 nm. This composite structure provides the necessary electrical characteristics for memory operation at ultra-small scales where conventional transistors fail
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high integration density and large memory capacity by simplifying the circuit and preventing errors from interference currents between cells, while maintaining a self-rectifying characteristic without additional rectifying elements, thus overcoming the limitations of existing technologies.
Implementation Method 1
a dielectric layer which has resistance and capacitance changed by a tunneling conduction phenomenon of charges according to an applied voltage
Implementation Method 2
an active layer which has resistance and capacitance changed according to an applied voltage
Data Source
AI summary
A nonvolatile memory device having multi-level resistance and capacitance values is provided. Such a nonvolatile memory device includes: a substrate; a first electrode that is provided on the substrate; a dielectric layer that is provided on the first electrode, has resistance and capacitance changed by a tunneling conduction phenomenon of charges according to an applied voltage, has rectifying characteristics, and includes a dielectric material; an active layer that is provided on the dielectric layer, has resistance and capacitance changed according to an applied voltage, and includes a graphene oxide complex; and a second electrode that is provided on the active layer. In addition, the nonvolatile memory device has multi-level resistance and capacitance values according to an applied voltage.