Planar Graphene Transistor Layout to Avoid Transfer Defects
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Solution Overview
Problem
Current methods for manufacturing graphene transistors fail to fully realize the potential of graphene's electronic properties due to defects and non-uniformity introduced during the manufacturing process, particularly when transferring graphene onto substrates with non-planar surfaces, leading to reduced reliability and performance.
Innovation Solution
A method involving a substrate with a substantially flat surface, comprising both insulating and semiconducting regions, where a graphene layer is directly deposited using MOCVD, ensuring a continuous and defect-free interface, and a dielectric layer is formed on the semiconducting region with source, gate, and drain contacts strategically placed to modulate current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If graphene is transferred onto pre-patterned substrates with non-planar surfaces, then the transistor structure can be formed, but defects and non-uniformity are introduced that reduce electronic properties
Solution Approach 1:
Instead of transferring graphene onto pre-patterned substrates (conventional approach), the patent inverts the process by first forming a continuous graphene layer on a planar substrate, then patterning the underlying substrate to create insulating and semiconducting regions. This inversion eliminates transfer-induced defects while achieving the required transistor structure.
Solution Approach 2:
The patent performs preliminary graphene deposition on a planar substrate before substrate patterning. This preliminary action ensures a defect-free continuous graphene layer is established first, preventing subsequent processing steps from introducing defects that would occur with transfer methods.
2Adaptability or versatility
If graphene is deposited on a non-planar substrate surface, then the transistor components can be integrated, but the graphene layer uniformity and electronic properties deteriorate
Solution Approach 1:
The patent reverses the conventional sequence by depositing graphene on a planar substrate first, then creating the non-planar substrate structure underneath. This allows component integration while preserving graphene layer uniformity, as the graphene is deposited before the substrate is patterned into insulating and semiconducting regions.
3Ease of manufacture
If transfer processes are used to place graphene on substrates, then the transistor can be assembled, but defects are introduced that reduce device performance
Solution Approach 1:
The patent extracts the problematic transfer step from the manufacturing process entirely. By depositing graphene directly on the substrate in situ before patterning, the method eliminates transfer-induced defects while maintaining ease of manufacture through a streamlined single-substrate process.
Solution Approach 2:
Graphene deposition is performed as a preliminary action before substrate patterning and device assembly. This preliminary deposition on a planar surface ensures high-quality graphene formation, and subsequent processing steps integrate the transistor components without compromising the graphene layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a graphene transistor with improved electronic properties, including a stable Ion/Ioff ratio, reduced defects, and enhanced reliability by maintaining the graphene's integrity and uniformity, allowing for better control of current flow and increased switching frequencies.
Implementation Method 1
forming a graphene layer structure on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region
Data Source
AI summary
The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.