Graphics Processor A-Barriers for Non-Blocking Async Synchronization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing graphics processing units (GPUs) face challenges in efficiently synchronizing asynchronous operations across multiple threads, particularly in single instruction, multiple data (SIMT) architectures, which can lead to inefficiencies in parallel processing.

Innovation Solution

The introduction of addressable barriers (A-barriers) as hardware-supported synchronization objects to track and coordinate asynchronous operations, such as asynchronous matrix multiply and accumulate (MMA) and direct memory access (DMA), enabling low-latency and high-bandwidth data sharing across work-items and threads in a graphics core cluster.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional barrier and synchronization mechanisms are used in SIMT architectures, then thread synchronization is achieved, but processing efficiency and performance deteriorate due to blocking operations

Engineering Contradiction:

Improvethread synchronizationVSAvoidprocessing efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent introduces addressable barriers as hardware-supported intermediary objects that mediate between threads and asynchronous operations. These barriers act as synchronization points that threads can wait on without blocking the entire processing pipeline, allowing other threads to continue execution while maintaining proper synchronization order.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional software-based barrier mechanisms with hardware-supported addressable barriers. This substitution eliminates the need for complex software polling and waiting loops, reducing CPU overhead and enabling more efficient parallel execution while maintaining synchronization guarantees.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If asynchronous operations are implemented without dedicated synchronization objects, then parallel processing throughput is improved, but synchronization reliability deteriorates

Engineering Contradiction:

Improveparallel processing throughputVSAvoidsynchronization reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements addressable barriers that are initialized and configured before asynchronous operations begin. These pre-configured barriers establish synchronization points in advance, allowing the system to maintain high throughput while ensuring that all necessary synchronization conditions are met before operations proceed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The hardware-supported addressable barriers automatically manage synchronization state and coordination without requiring explicit software intervention. The barriers self-manage the synchronization protocol, tracking asynchronous operation completion and coordinating thread execution, which maintains reliability while minimizing overhead.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250291756A1Graphics processor addressable barriers

Publication Date: 2025.09.18 INTEL CORP

AI summary

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including a plurality of processing elements, a distributed shared memory coupled with the plurality of processing elements, and barrier circuitry within each of the plurality of graphics cores. The barrier circuitry include memory to store a plurality of addressable multi-phase barriers that enable synchronization of a plurality of different types of asynchronous operations within the graphics core cluster.