3D Memory Graphite Strip Layout for Higher Layer Density
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Solution Overview
Problem
Two-dimensional memory arrays are reaching scaling limits, hindering further increases in memory density, and existing three-dimensional memory arrays face challenges in efficiently forming high-density structures due to limitations in etching conductive layers.
Innovation Solution
The use of graphite or carbon-based materials for conductive layers in three-dimensional memory arrays, allowing for easier etching and forming more layers, with methods involving graphene or nanocrystalline graphite, and specific deposition processes to create horizontal and vertical conductive strips for increased density and efficient memory cell addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional conductive materials are used in 3D memory arrays, then memory density can be increased by stacking layers, but etching difficulty increases and manufacturing complexity worsens
Solution Approach 1:
The patent changes the material parameter from traditional metals (铜, 铝) to graphite, which has different etching properties. Graphite can be selectively removed by oxygen plasma etching while leaving metal interconnect layers intact, enabling precise formation of memory cell structures without damaging other components.
Solution Approach 2:
The patent employs a composite structure where graphite conductive layers are combined with metal interconnect layers in a stacked configuration. This composite approach allows each material to perform its optimal function: graphite for selective etching and memory cell formation, metals for low-resistance electrical interconnection.
2Quantity of substance
If more layers are stacked to increase memory density, then area density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces dielectric layers as intermediary materials between the graphite conductive layers and metal interconnect layers. These dielectric layers serve as spacers and alignment references, facilitating precise positioning of subsequent layers and maintaining manufacturing precision as the number of stacked layers increases.
3Ease of manufacture
If graphite conductive layers are used, then etching ease improves and more layers can be formed, but material selection constraints increase
Solution Approach 1:
The patent segments the conductive structure into distinct functional layers: graphite layers for memory cell formation (easy to etch) and metal layers for interconnection (low resistance). This segmentation allows each material to be optimized for its specific function while maintaining overall manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density three-dimensional memory arrays with improved etching capabilities, allowing for more layers and increased area density, facilitating efficient memory cell formation and addressing, thereby overcoming the scaling limitations of two-dimensional arrays.
Implementation Method 1
specific deposition processes to create horizontal and vertical conductive strips
Data Source
AI summary
A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.