Grid-like MOS Transistor Metal Wiring Layout
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Solution Overview
Problem
Conventional grid-like transistors experience increased parasitic resistance in metal wiring, leading to higher overall on-resistance and reduced drive capacity due to varying wire widths and layout limitations, which hinders the downsizing of electronic circuits and efficiency of gate width per unit area.
Innovation Solution
The semiconductor device features a grid-like transistor with rectangular source and drain regions arranged in a checkered pattern, where metal wirings are aligned along the grid direction and connected via contacts, ensuring uniform width and reduced parasitic resistance by forming source and drain metal wirings in a zigzag pattern to cover the gate electrode, thereby minimizing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal wirings are formed with varying widths to connect source and drain regions in grid-like transistors, then layout flexibility is improved, but parasitic resistance increases
Solution Approach 1:
The patent applies local quality by forming metal wirings with different widths in different regions: wider widths in regions where diagonal connections are needed and narrower widths where straight connections suffice. This localized variation in wiring width optimizes both layout flexibility and parasitic resistance by matching the wiring geometry to the specific connection requirements of each region.
Solution Approach 2:
The patent resolves the contradiction by transitioning from two-dimensional planar wiring to three-dimensional wiring structures, including vias that connect different metal layers. This dimensional change allows diagonal connections to be achieved through vertical stacking rather than horizontal routing, reducing the need for width variations and minimizing parasitic resistance while maintaining layout flexibility.
2Area of moving object
If grid-like transistor structure is used to raise gate width efficiency, then circuit downsizing is achieved, but overall on-resistance increases due to metal wiring resistance
Solution Approach 1:
The patent applies composite materials by combining multiple metal layers with different properties and configurations. The first metal layer provides local connections with optimized width variations, while the second metal layer provides global interconnections. This composite wiring structure reduces overall parasitic resistance by distributing current paths across multiple materials and layers, thereby maintaining low on-resistance despite the high-density grid-like transistor layout.
3Quantity of substance
If source and drain regions are arranged in high density, then circuit integration is improved, but diagonal wiring becomes impossible due to layout limitations
Solution Approach 1:
The patent resolves the connectivity limitation in high-density layouts by introducing a third dimension through vias and multiple metal layers. Diagonal connections that cannot be achieved in the planar first metal layer are realized by routing through vias to the second metal layer, enabling flexible connectivity patterns regardless of transistor density in the underlying layer.
Data Source
AI summary
A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.