Groove-Based Interconnect Plating for High Current Capacity
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Solution Overview
Problem
Current interconnect structures face challenges in increasing current capacity without compromising miniaturization or requiring increased plating thickness, which hinders productivity and signal line miniaturization.
Innovation Solution
The interconnect structure features a resin layer with parallel grooves where the plating film is formed on both the resin layer's surface and the inner walls of the grooves, enhancing current capacity without increasing plating thickness, thus allowing for reduced plating time and maintaining miniaturization capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of interconnects is increased to enhance current capacity, then the current carrying capability is improved, but the plating time is extended and miniaturization is precluded
Solution Approach 1:
The invention transitions from increasing interconnect thickness (one-dimensional solution) to utilizing groove structures that extend the conductive path along the inner walls (adding dimensional complexity). The plating film is formed not only on the resin layer surface but also on the inner wall surfaces of grooves, effectively increasing the current-carrying cross-section without increasing overall thickness, thereby reducing plating time while maintaining miniaturization capability.
Solution Approach 2:
The resin layer is divided into multiple grooves that create segmented conductive paths. Each groove contains a plating film that contributes to the overall current capacity. This segmentation allows the current to flow through multiple parallel paths along the groove inner walls, increasing total current capacity without requiring a single thick interconnect, thus reducing the plating thickness needed.
2Quantity of substance
If the thickness of interconnects is increased to enhance current capacity, then the current carrying capability is improved, but miniaturization of signal lines is prevented
Solution Approach 1:
Instead of increasing interconnect width or thickness in the traditional planar dimensions, the invention utilizes the vertical dimension by forming grooves and depositing plating on the inner wall surfaces. This creates a three-dimensional conductive structure that increases current capacity without expanding the footprint or requiring thicker overall plating, thereby enabling continued miniaturization of signal lines.
Solution Approach 2:
The plating film is nested within the groove structures, with the conductive material positioned inside the grooves rather than expanding outward. This nested configuration increases the effective current-carrying cross-section by utilizing the groove volume, allowing higher current capacity within the same planar footprint, thus supporting miniaturization.
3Quantity of substance
If the number of conductive layers in a multilayer board is increased to enhance current capacity, then the current carrying capability is improved, but the device complexity is increased
Solution Approach 1:
Instead of uniformly increasing the number of conductive layers throughout the multilayer board, the invention applies the groove structure locally only in areas where high current capacity is required. The grooves are formed in specific regions corresponding to power supply interconnects, while signal lines can maintain simpler structures, thus enhancing current capacity without proportionally increasing overall device complexity.
Solution Approach 2:
The resin layer is segmented into multiple grooves that create parallel conductive paths within a single layer. This segmentation provides an alternative to adding multiple layers, as the multiple groove structures within one layer can collectively carry high current, thereby reducing the need to increase the number of conductive layers and the associated device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases current capacity while reducing plating time and preventing hindrances to signal line miniaturization, thereby enhancing productivity and reducing heat generation during current conduction.
Implementation Method 1
interconnects are formed of a plating film created on a resin layer front surface in the area in which the interconnects are formed and on inner wall surfaces of the plurality of grooves
Data Source
AI summary
An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.