Grooved Semiconductor Package Structure for Low-Height Die Stability
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Solution Overview
Problem
Current 3D semiconductor packaging technologies face challenges in reducing package height and improving reliability due to slight translocation of chips during movement or vibration, leading to poor performance and reliability issues.
Innovation Solution
A method involving a substrate wafer with grooves and electrically conductive pillars, where semiconductor die stacks are placed in the grooves and sealed with an insulating dielectric layer, reducing package height and preventing translocation through the insulating dielectric layer's fixation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more chips are stacked in a single package to meet high capacity and high function requirements, then the functionality and capacity of the electronic components are improved, but the package height increases
Solution Approach 1:
The patent transitions from vertical stacking (increasing height in the Z-direction) to lateral arrangement within grooves on the substrate surface (utilizing X-Y plane space). Multiple semiconductor dies are positioned side-by-side in grooves rather than stacked vertically, thereby achieving high capacity and functionality while maintaining a low package height.
2Adaptability or versatility
If chips are arranged in a stacked configuration to increase capacity, then more functions can be integrated, but slight translocation occurs during movement or vibration resulting in poor reliability
Solution Approach 1:
The patent divides the substrate surface into multiple grooves that separately accommodate individual semiconductor dies or die stacks. Each die is independently positioned within its own groove, preventing relative movement between adjacent dies during vibration or shock, thereby improving reliability while maintaining high capacity through parallel arrangement of multiple segmented units.
Solution Approach 2:
The insulating dielectric material serves as an intermediary substance that fills the grooves and surrounds the semiconductor dies, providing mechanical support and fixation. This dielectric material prevents translocation of the dies during movement or vibration while also providing electrical insulation, thereby enhancing both reliability and electrical performance.
3Adaptability or versatility
If conventional stacking technology is used to achieve high capacity, then more chips can be incorporated, but the package structure experiences warpage that negatively affects performance
Solution Approach 1:
The patent redistributes multiple semiconductor dies laterally across the substrate surface in grooves rather than concentrating them in vertical stacks. This lateral distribution balances the mass and stress distribution across the substrate, reducing warpage while achieving high capacity through increased die count in the planar direction.
Data Source
AI summary
Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.