Ground Circuitry for Semiconductor Memory Devices
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Solution Overview
Problem
In semiconductor memory devices, the interconnect resistance and capacitance of bit and source lines increase with length, causing voltage variations across memory cells in the array, leading to inconsistent data writing and erasing operations.
Innovation Solution
The implementation of first and second ground circuits, each comprising transistors connected to bit and source lines respectively, allows these lines to be grounded closer to their endpoints, reducing interconnect resistance and capacitance and ensuring equal voltages are applied to memory cells independently of their location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bit lines and source lines are grounded outside the memory cell array, then the structure is simple and easy to manufacture, but the interconnect resistance and capacitance increase with distance from the grounding point, causing voltage variations across memory cells
Solution Approach 1:
The patent divides the single external grounding point into multiple local grounding circuits distributed throughout the memory cell array. Each grounding circuit includes transistors that connect bit lines and source lines to ground at multiple locations, segmenting the long interconnect paths into shorter sections with lower resistance and capacitance.
Solution Approach 2:
The patent introduces local grounding circuits at specific locations within the memory cell array rather than using a uniform external grounding approach. These local grounding circuits are strategically placed to compensate for voltage drops in specific regions, providing non-uniform grounding that adapts to the local electrical characteristics of different parts of the array.
2Manufacturing precision
If grounding circuits are added within the memory cell array, then voltage uniformity across memory cells is improved, but the device complexity and transistor count increase
Solution Approach 1:
The grounding transistors in the patent serve multiple functions: they act as switching elements for the grounding operation, as selection transistors for activating specific grounding circuits, and as part of the overall memory cell structure. This multi-functionality reduces the need for separate dedicated grounding components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the grounding function with the existing memory cell transistor structure. The grounding transistors are integrated into the same layout and process as the memory cell transistors, sharing common interconnect layers and ground lines. This integration approach combines the grounding circuit with the memory array structure, reducing overall device complexity.
3Manufacturing precision
If multiple grounding points are distributed throughout the memory cell array, then interconnect resistance and capacitance are reduced, but the layout uniformity and manufacturing complexity increase
Solution Approach 1:
The patent employs asymmetric grounding circuit designs where the grounding transistors and associated structures are strategically positioned to compensate for the asymmetric voltage drops that occur in rectangular memory arrays. The grounding circuits are placed and sized differently in different regions to match the non-uniform current distribution and interconnect characteristics of the array.
Solution Approach 2:
The patent uses the grounding circuits to create equipotential regions throughout the memory cell array. By distributing grounding points and using transistors to connect bit lines and source lines to ground at multiple locations, the patent maintains approximately equal potential across different parts of the array, compensating for the inherent voltage drops in long interconnect lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures that memory cells receive consistent voltages for writing and erasing operations, improving data accuracy and maintaining the uniformity of the memory cell array layout without degrading the characteristics of the memory cells.
Implementation Method 1
Bit lines and source lines each have an interconnect resistance and an interconnect capacitance, and the interconnect resistance and the interconnect capacitance increase with increasing length of the line
Implementation Method 2
a first ground circuit configured to ground the bit lines together in accordance with a received first signal, and a second ground circuit configured to ground the source lines together in accordance with a received second signal
Data Source
AI summary
A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.