Ground Selection Transistor Programming for Word-Line Interference Control
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Solution Overview
Problem
The increased integration of memory devices leads to interference between word lines, string selection lines, and ground selection lines, reducing the reliability of data storage.
Innovation Solution
A memory device design with differently programmed ground selection transistors and dummy transistors, controlled by a logic that alternates threshold voltages during erase and program cycles, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory devices is enhanced by increasing the number of word lines stacked in a vertical direction, then the capacity of memory devices increases, but interference between word lines, string selection lines, and ground selection lines increases, reducing data reliability
Solution Approach 1:
The patent applies local quality by programming ground selection transistors with different threshold voltages (first threshold voltage for some transistors, second threshold voltage higher than the first for other transistors) to create differentiated operational characteristics in specific regions. This allows certain transistor groups to operate under different erase cycle conditions, reducing cumulative interference effects in high-density vertical structures while maintaining overall capacity.
Solution Approach 2:
The patent implements dynamics by controlling erase operations on ground selection transistors at every N erase/program cycles from a first time point, creating a periodic maintenance rhythm. This dynamic periodic erasing prevents permanent threshold voltage shifts and reduces cumulative interference effects in vertically stacked word lines, thereby maintaining data reliability as integration degree increases.
2Productivity
If the degree of integration of memory devices is enhanced, then the number of word lines stacked in a vertical direction increases, but interference between lines increases, making continuous threshold voltage monitoring more complex and resource-intensive
Solution Approach 1:
The patent applies partial action by selectively programming only some ground selection transistors with the first threshold voltage and others with the second threshold voltage, rather than uniformly programming all transistors. This partial differentiation reduces the monitoring burden by creating distinct operational groups that can be managed with simpler control logic, enabling higher integration without proportionally increasing monitoring complexity.
Solution Approach 2:
The patent implements periodic action by performing erase operations on ground selection transistors at every N erase/program cycles rather than continuously. This periodic maintenance approach reduces the frequency of threshold voltage monitoring and adjustment operations, thereby lowering device complexity while still preventing cumulative interference effects in high-density vertical word line structures.
Data Source
AI summary
A memory device includes a plurality of cell blocks, each of the cell blocks including a memory cell array including a plurality of cell strings, connected in parallel between a bit line and a common source line, and a control logic. At least one of the plurality of cell blocks includes a plurality of ground selection transistors connected to a corresponding plurality of special word lines. The control logic performs an erase operation on a first subset of the plurality of ground selection transistors at every N number of erase/program (E/P) cycles from a first time point and then programs the first subset of the plurality of ground selection transistors to a first threshold voltage, and may perform an erase operation on a second subset of the plurality of ground selection transistors and then program the second subset of the plurality of ground selection transistors to a second threshold voltage.