Group Word Line Erase for 3D Non-Volatile Memory Uniformity
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Solution Overview
Problem
3D stacked non-volatile memory devices face challenges in achieving uniform erase depth and speed due to variations in channel potential and memory hole diameter, leading to impacted data retention and erase performance.
Innovation Solution
The implementation of group word line erase and erase-verify methods, where storage elements are assigned to groups and control gate voltages are adjusted to equalize erase speed, and an erase-verify test is performed on a per-group basis to inhibit further erasing of completed elements, allowing resources to be redirected to unfinished elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional erase methods are used in 3D stacked non-volatile memory, then erase operation can be performed, but uniform erase distribution is not achieved due to variations in channel potential and memory hole diameter
Solution Approach 1:
The patent segments the memory device into multiple groups (first group and second group) based on their spatial location and electrical characteristics. Different erase voltages are applied to different groups, allowing customized erase operations for each segment. This segmentation enables uniform erase distribution across the 3D stacked memory by compensating for variations in channel potential and memory hole diameter through group-specific voltage adjustment.
Solution Approach 2:
The patent applies local quality by assigning different erase voltages to different groups of memory cells based on their specific electrical characteristics and spatial positions. The first group receives a first erase voltage while the second group receives a second erase voltage, creating localized erase conditions optimized for each group's characteristics. This local differentiation ensures uniform erase distribution across the entire memory device despite variations in channel potential and memory hole diameter.
2Productivity
If higher erase voltage is applied to increase erase speed, then erase operation completes faster, but non-uniform erasure occurs due to potential drop variations
Solution Approach 1:
The patent changes the erase voltage parameter across different groups to achieve both high erase speed and uniform erase distribution. By applying a first erase voltage to the first group and a second erase voltage to the second group, the system optimizes erase speed for each group while maintaining uniformity across the entire memory device. This parameter differentiation allows the erase operation to complete faster than conventional uniform voltage methods while preventing non-uniform erasure.
3Device complexity
If all storage elements are erased simultaneously, then erase operation is simple, but completed erasures cannot assist ongoing erasure processes
Solution Approach 1:
The patent implements preliminary action by performing erase-verify tests on the first group before completing the erase operation on the second group. The first group is erased and verified first, and its completed erasure state can assist the ongoing erase process of the second group. This staged approach maintains relatively simple control logic while significantly improving overall erase speed through the assistance effect between groups.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a tightened erase distribution, enhanced erase speed, improved channel potential boosting, and increased reliability by compensating for variations in potential drop and memory hole diameter.
Implementation Method 1
they lack a p-well substrate and rely on gate-induced drain leakage for erasing
Data Source
AI summary
An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.