Guard Active Regions for Semiconductor Shallow Trench Isolation
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Solution Overview
Problem
In semiconductor devices, the variation in stress at the border between cell isolation regions and peripheral isolation regions due to inferior film-burying performance of HDP-CVD leads to uneven word trench widths, affecting transistor characteristics and potentially causing short circuits.
Innovation Solution
The introduction of guard active regions formed from the semiconductor substrate, which encircle the memory cell area and isolate the peripheral isolation region from cell isolation regions, preventing stress development and maintaining even word trench widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If HDP-CVD is used to form isolation regions with large width in peripheral circuit area, then productivity is improved, but film-burying performance deteriorates causing insufficient filling of narrow trenches
Solution Approach 1:
The patent applies different dielectric films to different regions: HDP-CVD dielectric film for peripheral isolation regions (large width) and flowable CVD dielectric film for cell isolation regions (narrow trenches). This local differentiation allows each region to receive the most appropriate film type for its specific requirements, resolving the contradiction between productivity and film-burying performance.
2Device complexity
If cell isolation regions and peripheral isolation regions integrate at the border, then device structure is simplified, but stress variation causes uneven word trench widths affecting transistor characteristics
Solution Approach 1:
The patent introduces a guard ring structure as an intermediary element between the cell isolation regions and peripheral isolation regions. This guard ring acts as a buffer that prevents stress from the peripheral isolation region from directly affecting the cell isolation regions, thereby maintaining uniform word trench widths while still allowing the overall device structure to remain relatively simple.
Solution Approach 2:
The patent segments the isolation structure by introducing a guard ring that divides the border region between cell and peripheral isolation regions. This segmentation isolates the stress-prone interface, preventing stress transmission from the peripheral region to the cell region, thus maintaining manufacturing precision while managing device complexity.
3Area of moving object
If narrow trenches of 30 nm or less are formed in memory cell area, then device integration density is improved, but HDP-CVD cannot fill trenches sufficiently due to inferior film-burying performance
Solution Approach 1:
The patent selectively applies flowable CVD dielectric film to the cell isolation regions where narrow trenches (30 nm or less) are present, while using HDP-CVD dielectric film for peripheral regions. The flowable CVD process provides superior film-burying performance that ensures sufficient filling of the narrow trenches, enabling high device integration density without compromising manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the operation of semiconductor devices by preventing variations in word line positions and reducing the risk of short circuits between word lines and bit lines.
Implementation Method 1
a dielectric film formed by HDP (High Density Plasma)-CVD (Chemical Vapor Deposition)
Implementation Method 2
a flowable thin film formed by flowable CVD
Data Source
AI summary
A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c.