Guided Semiconductor Wafer Defect Inspection via Pattern Analysis
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Solution Overview
Problem
Current semiconductor wafer inspection systems fail to effectively distinguish between systematic and random defects, leading to inefficient detection and review of flaws in the fabrication process, which can result in lower yields due to unresolved design or process flaws.
Innovation Solution
A guided inspection system that uses a processing device to identify candidate defects on a semiconductor wafer by analyzing optical images and design data, determining if they are systematic or random based on pattern association and combined defect probability scores, and selectively sending systematic defects to a defect review tool for further analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed inspection of all candidate defects is performed, then defect detection completeness is improved, but inspection time and processing efficiency deteriorate
Solution Approach 1:
The inspection system segments defects into two categories: systematic defects (associated with patterns in design data) and random defects (not associated with patterns). This segmentation allows the system to apply different inspection strategies to different defect types, reviewing systematic defects in detail while quickly identifying random defects, thereby reducing overall inspection time while maintaining detection completeness.
Solution Approach 2:
The system applies different inspection quality levels to different defect locations based on their association with design patterns. Defects located at positions corresponding to patterns in design data receive thorough review (high local quality), while defects not associated with patterns receive minimal review (low local quality). This localized quality approach optimizes inspection resources while maintaining necessary detection accuracy.
2Measurement precision
If all candidate defects are reviewed by defect review tool, then defect analysis accuracy is improved, but processing efficiency and productivity deteriorate
Solution Approach 1:
The system extracts and identifies only systematic defects (those associated with patterns in design data) for detailed review by the defect review tool, while excluding random defects from thorough review. This extraction approach ensures that processing resources are concentrated on defects that are most likely to indicate systematic fabrication issues, thereby maintaining high analysis accuracy for critical defects while improving overall processing efficiency.
Solution Approach 2:
The system performs preliminary classification of defects based on their association with design patterns before sending them to the defect review tool. By pre-identifying systematic defects through pattern matching, the system prepares a filtered list of high-priority defects for review, eliminating the need for comprehensive review of all defects and thus improving productivity while maintaining accuracy for systematic issues.
3Measurement precision
If systematic defects are identified through pattern association, then defect classification accuracy is improved, but system complexity deteriorates
Solution Approach 1:
The system introduces design data as an intermediary element to bridge the connection between physical defect locations and their classification. By comparing defect positions against pattern information from design data, the system achieves accurate systematic defect identification without requiring complex analysis of defect characteristics alone. The design data serves as a reference mediator that simplifies the classification process while improving accuracy.
Data Source
AI summary
A candidate defect may be identified at a semiconductor wafer. A determination may be made as to whether the candidate defect at the semiconductor wafer corresponds to a systematic defect or a random defect. In response to determining that the candidate defect at the semiconductor wafer corresponds to a systematic detect, the candidate defect at the semiconductor wafer may be provided to a defect review tool for review by the defect review tool.