Guiding Pattern Package Structure for Void-Free Underfill Flow
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Solution Overview
Problem
The challenge in semiconductor packaging lies in effectively managing the flow of underfill material to prevent void formation during the encapsulation process, particularly in high-density areas where different pitch arrangements of conductive terminals create flow resistance and void entrapment.
Innovation Solution
Incorporation of guiding patterns, such as dot-shaped or strip-shaped structures, between die bonding regions on the interposer wiring substrate to provide capillary guidance for the underfill material, ensuring uniform flow and minimizing voids by controlling the flow front and path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If underfill material is applied between semiconductor dies and substrate, then die attachment is enhanced and mechanical stress is reduced, but voids form in the underfill material due to varying density areas and flow resistance
Solution Approach 1:
Guiding patterns are introduced as intermediary structures between the underfill material and the substrate/dies interface. These patterns provide capillary forces that guide the flow of underfill material, ensuring uniform distribution and preventing void formation in high-density terminal areas. The guiding patterns act as a mediator that controls the fluid dynamics of underfill application.
Solution Approach 2:
The guiding patterns are strategically placed in specific locations where void formation is most problematic, particularly in areas with high-density conductive terminals. The patterns have varying densities and configurations tailored to local flow resistance characteristics, providing localized control over underfill material distribution to eliminate voids while maintaining overall package reliability.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but packaging complexity and difficulty increase
Solution Approach 1:
The substrate surface is segmented into different regions with varying guiding pattern densities corresponding to different conductive terminal densities. High-density terminal areas receive higher-density guiding patterns, while low-density areas receive lower-density patterns. This segmentation allows the packaging structure to adapt to local integration density requirements without increasing overall complexity.
3Power
If conductive terminals are densely arranged to increase bandwidth and speed, then performance improves, but shearing stress on terminals increases
Solution Approach 1:
The guiding patterns serve as intermediary structures that distribute mechanical stress from the underfill material away from the conductive terminals. By providing a controlled flow path and support structure, the guiding patterns reduce the direct shear stress transmitted to densely packed terminals, enabling high-density arrangements without compromising terminal reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The guiding patterns enhance the flow of underfill material, reducing the likelihood of void formation and enhancing the reliability of conductive terminals by ensuring complete encapsulation and minimizing shear stress.
Implementation Method 1
The introduction of guiding patterns on the interposer wiring substrate, which are electrically insulated from semiconductor dies and conductive terminals, helps control the flow of underfill material by providing capillary guiding forces
Data Source
AI summary
A package structure including a wiring substrate, semiconductor dies, and a dielectric layer is provided. The wiring substrate includes die bonding regions and guiding patterns (auxiliary patterns, or dummy patterns) distributed between the die bonding regions. The semiconductor dies are disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies. The dielectric layer is disposed the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns.