Digital Gyroscope Jitter Noise Cancellation Using Sampled Drive Signal
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Solution Overview
Problem
MEMS gyroscopes face significant noise degradation due to large quadrature signals, which require a clock signal with minimal jitter to avoid noise folding, making direct sampling challenging and power-intensive.
Innovation Solution
A digital gyroscope circuit that subtracts the sampled drive signal from the sampled rate signal to eliminate clock jitter-induced noise, relaxing the noise requirements for the oscillator and allowing for a low-power phase-locked loop implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If direct sampling of gyroscope output is used, then the system can operate with simpler architecture, but clock jitter induces noise folding that degrades measurement precision
Solution Approach 1:
The patent extracts and removes the quadrature signal component from the sampled output before digital processing. By separating the quadrature signal (which contains the clock jitter noise) from the in-phase signal (containing the desired rate information), the system eliminates the noise folding problem while maintaining direct sampling architecture simplicity.
Solution Approach 2:
The patent introduces an intermediary digital signal processing stage that applies a notch filter or quadrature cancellation technique between the ADC and the final output. This intermediary processing removes the clock jitter-induced noise without requiring a perfectly low-jitter clock, thus resolving the contradiction between simple architecture and high precision.
2Measurement precision
If a clock signal with very small jitter is used, then noise folding is avoided and measurement precision is maintained, but power consumption increases due to stringent oscillator requirements
Solution Approach 1:
The patent converts the harmful effect of clock jitter into a removable artifact by sampling the quadrature signal. The clock jitter noise that would normally corrupt the measurement is instead captured in the quadrature component, which is then digitally removed. This allows the use of lower-power oscillators with higher jitter that would otherwise be unacceptable.
Solution Approach 2:
The patent changes the parameter of clock jitter tolerance by moving the noise rejection function from the analog oscillator domain to the digital signal processing domain. This parameter change allows the oscillator to operate at lower power with higher jitter, while the digital processing restores the required measurement precision.
3Ease of manufacture
If quadrature signal is present in the output, then the gyroscope can be manufactured with standard processes, but the quadrature signal folds close-in phase noise into the signal band degrading measurement precision
Solution Approach 1:
The patent extracts the quadrature signal component containing the folded noise and removes it from the measurement path. By separating and eliminating the quadrature component digitally, the system maintains the manufacturing simplicity of having a quadrature signal while removing its harmful noise-folding effect.
Solution Approach 2:
The patent employs a feedback mechanism where the quadrature signal is monitored and used to generate a correction signal that is subtracted from the in-phase signal path. This feedback loop continuously cancels the noise folding effect, allowing standard manufacturing processes to be used without compromising measurement precision.
Data Source
AI summary
In a digital gyroscope, the rate signal (including the quadrature) and the displacement signal of the drive part are sampled with an ADC. This displacement signal has the same frequency and phase as the quadrature signal that gets sampled in the rate channels. The displacement signal is sampled with the same clock as the rate signal resulting in the displacement signal having the same close-in phase noise folded into the signal band as the sampled quadrature in the rate signal. The sampled drive signal is subtracted from the sampled rate signal to eliminate the clock jitter induced noise in the rate signal. This relaxes the close-in phase noise requirement of the PLL and allows for a low power PLL implementation.