Hafnium Silicon Oxynitride Interlayer for Non-Volatile Memory Leakage Control
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Solution Overview
Problem
The integration of non-volatile memory devices faces challenges with parasitic capacitance due to insufficient space between floating gate electrode layers, which is exacerbated by the limitations of using a high-k dielectric layer as an intergate insulation layer, leading to increased leakage current and phase separation issues.
Innovation Solution
A method involving the formation of hafnium-rich or zirconium-rich silicon oxide and oxynitride layers through nitridation processes to create a thin effective oxide layer, preventing leakage current deterioration by controlling nitrogen atom coupling rates and using specific deposition techniques like plasma nitridation and rapid thermal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of the intergate insulation layer is reduced to decrease parasitic capacitance, then the coupling ratio is improved, but the leakage current increases rapidly
Solution Approach 1:
The patent changes the material parameter of the intergate insulation layer from conventional oxide/nitride/oxide (ONO) structure to high-k dielectric material. This parameter change allows achieving the same electrical insulation effect with a thinner physical layer, thereby reducing parasitic capacitance while maintaining acceptable leakage current characteristics through the high-k material's inherent properties
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including high-k dielectric layer, silicon oxide layer, and silicon nitride layer. This composite material approach combines the advantages of high-k material (low parasitic capacitance) with protective layers that prevent degradation, thereby resolving the contradiction between reducing thickness and controlling leakage current
2Manufacturing precision
If a high-k dielectric layer is used as the intergate insulation layer to reduce effective oxide thickness, then the coupling ratio is improved, but the leakage current properties deteriorate due to silicon oxide layer formation, crystallization, and phase separation
Solution Approach 1:
The patent applies preliminary protective actions by forming a silicon oxide layer and a silicon nitride layer before the high-k dielectric layer is exposed to subsequent thermal processes. These preliminary layers act as barriers that prevent silicon diffusion into the high-k layer during thermal processing, thereby preventing the formation of silicon oxide layers within the high-k material that would increase effective oxide thickness and degrade leakage current properties
Solution Approach 2:
The patent introduces cushioning layers (silicon oxide and silicon nitride) that absorb or prevent harmful effects before they can reach the high-k dielectric layer. These layers cushion against silicon diffusion and phase separation during thermal processing, maintaining the integrity and electrical properties of the high-k layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of non-volatile memory devices with improved intergate insulation, reducing leakage current and maintaining a sufficiently thin effective oxide layer thickness, thereby enhancing device performance and reliability.
Implementation Method 1
upon deposition of the high-k dielectric layer or subsequent thermal process, the high-k dielectric layer and the floating gate electrode layer pattern 120 are react to form a silicon oxide (SiO2) layer
Implementation Method 2
Second, crystallization of the high-k dielectric layer itself by the subsequent thermal process occurs and this may deteriorate the leakage current properties
Implementation Method 3
Third, phase separation of the high-k dielectric layer by the subsequent thermal process occurs and impurities are diffused into the high-k dielectric layer upon formation of the control gate layer electrode 140
Data Source
AI summary
A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.