Semiconductor Package Comprising Two Semiconductor Transistor Dies Connected Together to Form an Electrical Half-Bridge Circuit
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving fast switching of high currents and efficient heat dissipation due to long connection distances and inefficient heat dissipation mechanisms.
Innovation Solution
A semiconductor package design featuring a leadframe with interconnected semiconductor transistor dies forming a half-bridge circuit, utilizing a substrate with patterned connections and a direct copper bond (DCB) or similar materials, and an encapsulant for efficient heat dissipation, with leads extending outside the encapsulant for flexibility and stress absorption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor packages are used with standard encapsulation, then the device is protected and packaged, but parasitic inductances increase and switching speed decreases due to long connection distances
Solution Approach 1:
The patent transitions from conventional vertical stacking to a planar integrated structure where transistor dies are mounted on a substrate with patterned copper traces. This dimensional reorganization minimizes connection paths by keeping all connections within the same plane, reducing parasitic inductances and improving switching speed.
Solution Approach 2:
The patent merges the substrate, transistor dies, and copper traces into a single integrated assembly before encapsulation. This consolidation eliminates the need for separate connection components and reduces overall connection distance, directly addressing the switching speed limitation.
2Speed
If connection distances are reduced to improve switching speed, then parasitic effects decrease, but heat dissipation becomes more challenging due to concentrated thermal loads
Solution Approach 1:
The patent applies different material properties to different regions: the substrate provides mechanical support and electrical connectivity, while the encapsulant provides thermal management. The patterned copper traces concentrate current paths where needed, and the encapsulant distributes heat away from hot spots, addressing both switching speed and heat dissipation requirements.
Solution Approach 2:
The patent uses a composite structure combining the substrate, metal traces, semiconductor dies, and encapsulant material. This multi-material approach allows optimization of each component for its specific function: electrical connectivity for the copper traces, thermal management for the encapsulant, and mechanical support for the substrate.
3Reliability
If a common package with encapsulant is used, then all components are protected, but connection distances between components increase leading to parasitic effects
Solution Approach 1:
The patent performs the connection function preliminarily by creating patterned copper traces on the substrate before mounting the transistor dies. This pre-established connection network minimizes the distance signals must travel after assembly, reducing parasitic inductances while maintaining the protective encapsulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design minimizes parasitic inductances and enhances heat dissipation, improving board-level reliability and performance by reducing connection distances and optimizing heat transfer to external heat sinks.
Implementation Method 1
one or both of the substrate and the base plate is one of a direct copper bond (DCB), an active metal braze (AMB), or an insulated metal substrate (IMS)
Data Source
AI summary
A semiconductor package includes a leadframe comprising first leads and second leads, a substrate connected between the first leads and the second leads, a base plate, a first semiconductor transistor die connected between the base plate and the substrate and including a first source pad, a first drain pad, and a first gate pad, a second semiconductor transistor die connected between the base plate and the substrate and comprising a second source pad, a second drain pad, and a second gate pad, wherein the first semiconductor die and the second semiconductor die are interconnected to form a half-bridge circuit, wherein the first source pad of the first semiconductor die is electrically connected with the second drain pad of the second semiconductor die, an encapsulant embedding the first semiconductor die, the second semiconductor transistor die, and horizontal portions of the first leads and the second leads.