Half-Pumped SIMD Execution Unit Latency Reduction via Inversion
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Solution Overview
Problem
Conventional pipelined processor designs suffer from increased instruction execution time and issue-to-issue latency due to hazards and the limitations of result forwarding techniques, particularly in half-pumped SIMD execution units, which can lead to reduced performance and increased complexity.
Innovation Solution
The solution involves dynamically reversing the processing order of vector instruction operand slices based on the parity of the clock signal, allowing for K−1 cycle issue-to-issue latency without additional result forwarding buses, thereby improving performance and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional result forwarding techniques are used in half-pumped SIMD execution units, then instruction processing can continue without stalling, but issue-to-issue latency increases to K+1 cycles
Solution Approach 1:
The patent applies inversion by reversing the conventional processing order of vector operand slices. Instead of processing slices in the standard sequence (first slice then second slice), the execution unit processes the second slice before the first slice. This reversed processing order allows the execution unit to forward results to dependent instructions earlier, reducing issue-to-issue latency from K+1 cycles to K cycles while maintaining processing continuity.
2Loss of time
If additional result forwarding buses are added to reduce issue-to-issue latency, then latency can be reduced to K cycles, but device complexity increases
Solution Approach 1:
The patent eliminates the need for additional result forwarding buses by using inversion of the processing order. The existing result forwarding infrastructure is sufficient when combined with reversed slice processing sequence. By processing the second operand slice before the first operand slice, the execution unit can achieve K-cycle issue-to-issue latency using only the existing buses, thereby avoiding the complexity increase that would result from adding dedicated forwarding buses.
3Productivity
If half-pumped SIMD execution is used, then vector processing capability is improved, but issue-to-issue latency increases compared to fully pipelined execution
Solution Approach 1:
The patent maintains the productivity benefits of half-pumped SIMD execution while eliminating the latency penalty. By inverting the processing order of operand slices, the execution unit can forward results earlier in the pipeline. This allows half-pumped SIMD instructions to achieve the same K-cycle issue-to-issue latency as fully pipelined instructions, thereby preserving vector processing capability without the associated latency increase.
Data Source
AI summary
Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.