Half-Rate DFE Equalizer With Relaxed Feedback Timing
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Solution Overview
Problem
Conventional decision feedback equalizers (DFE) face challenges in implementing high-rate data streams due to stringent feedback delay requirements, which are difficult and expensive to achieve, especially in semiconductor processes, leading to limitations in equalizing high-speed data streams.
Innovation Solution
The proposed DFE circuit employs a half-rate architecture with cross-coupled equalization paths and uses feedback shift registers to relax feedback timing requirements, allowing for the equalization of higher rate data streams with reduced circuitry and energy consumption, and incorporates a serializer that converts data using quadrature phase clock signals to minimize circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional full-rate DFE architecture is used, then equalization performance is maintained, but feedback delay requirements become increasingly difficult and expensive to achieve at higher data rates
Solution Approach 1:
The patent divides the equalization function into two separate half-rate equalization paths instead of using a single full-rate path. Each path processes data at half the original rate, which relaxes the feedback delay requirements. The two paths are cross-coupled and their outputs are combined to achieve full-rate equalization performance, effectively segmenting the complex full-rate operation into manageable half-rate components.
2Productivity
If conventional serializers are used, then data conversion is achieved, but circuit area and power consumption increase
Solution Approach 1:
The patent merges the serialization function with the half-rate equalization paths by using the same latches and logic to perform both equalization and data conversion. The cross-coupled latches in the half-rate paths serve dual purposes: they provide feedback for equalization and simultaneously perform the serial conversion function, eliminating the need for separate serialization circuitry and reducing overall circuit area.
Solution Approach 2:
The equalization path circuitry is designed to perform multiple functions: it provides decision feedback equalization at half-rate and simultaneously performs serialization of the data stream. This multi-functional design eliminates redundant circuitry and reduces both area and power consumption while maintaining full operational capability.
Data Source
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AI summary
In described examples, a decision feedback equalizer (DFE) (100) includes a first summing node (112), a first synchronization latch (114), a second synchronization latch (116), a first feedback latch (118), and a first feedback shift register (120). The first summing node (112) is coupled to a data input of the DFE (100). The first synchronization latch (114) receives data from the first summing node (112). The second synchronization latch (116) and the first feedback latch (118) receive data from the first synchronization latch (114). The first feedback shift register (120) is coupled to an output of the second synchronization latch (116) or the first feedback latch (118). The first feedback shift register (120) includes sequentially coupled shift latches (122-128). A first of the shift latches (122) latches data received from the second synchronization latch (116) or the first feedback latch (118) and provides data to the first summing node (112).