Hammer-Shaped Separation Walls in Nanosheet FET Gate Patterning
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Solution Overview
Problem
The challenge in nanosheet field-effect transistors is the increased possibility of process defects due to down-scaling, which affects the speed and accuracy of integrated circuit devices, necessitating improved structural designs to enhance performance and reliability.
Innovation Solution
The integrated circuit device incorporates a novel structure with hammer-shaped or nail-shaped sheet separation walls between nanosheet stack structures, securing the patterning margin of gate electrodes and increasing the effective channel width, while using indent spacers to prevent leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional structures are used in nanosheet field-effect transistors, then manufacturing is simpler, but process defects increase and reliability decreases
Solution Approach 1:
The gate electrode structure is segmented into multiple gates (first gate electrode and second gate electrode) separated by sheet separation walls, allowing independent control of different nanosheet stack structures. This segmentation prevents process defects from affecting the entire device and improves reliability by isolating potential failure points.
Solution Approach 2:
Sheet separation walls are introduced as intermediary structures between adjacent nanosheet stack structures. These walls prevent direct interaction between neighboring structures, reducing cross-contamination and process defects during manufacturing while maintaining electrical isolation.
2Manufacturing precision
If sheet separation walls are added between nanosheet stack structures, then patterning margin is secured and manufacturing precision improves, but device complexity increases
Solution Approach 1:
Sheet separation walls are formed preliminarily before nanosheet stack structures are created. This preliminary action defines precise patterning boundaries in advance, ensuring that subsequent manufacturing steps can accurately form nanosheets with correct dimensions and spacing, thereby improving manufacturing precision.
Solution Approach 2:
The sheet separation walls provide localized structural features with specific geometries (including hammer-shaped configurations) that create distinct patterning zones. Each wall is designed with specific local properties to control the formation of adjacent nanosheet stacks, enabling precise local control without affecting the entire device.
3Reliability
If indent spacers are used to prevent leakage current, then transistor reliability improves, but manufacturing complexity increases
Solution Approach 1:
Indent spacers are extracted as separate, discrete components positioned between the nanosheets and sheet separation walls. By taking out this leakage prevention function as an independent element rather than integrating it into the main structure, the design allows for specialized optimization of the spacer geometry and material properties to maximize leakage blocking effectiveness.
4Productivity
If hammer-shaped sheet separation walls are used, then effective channel width is increased and performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The sheet separation walls are designed with asymmetric hammer-shaped geometries, featuring a wider head portion and a narrower body portion. This asymmetric design strategically places material distribution to maximize the effective channel width while maintaining manufacturability through standard patterning processes.
Solution Approach 2:
The hammer-shaped sheet separation walls introduce vertical dimensionality variations with different width profiles at different heights. The head portion extends wider than the body portion, creating a three-dimensional structure that increases effective channel width in the horizontal direction while using vertical stacking to achieve the shape, thereby improving performance without proportionally increasing lateral patterning complexity.
Data Source
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AI summary
An integrated circuit device (10) includes a hammer-shaped sheet separation wall (SW1, SW2) between nanosheet stack structures (NSS1, NSS2), thereby improving a patterning margin of a gate electrode (GE) and preventing or reducing an effective channel width from being decreased. That is, the integrated circuit device (10) may provide increased stable performance and improved reliability in a nanosheet field-effect transistor.