Multifunctional Handler System for Semiconductor Testing

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Solution Overview

Problem

Existing semiconductor device handlers face inefficiencies due to their 'last in, first out' loading sequence, integrated test chamber with loading and sorting units, and difficulty in maintaining constant temperature during testing, leading to operational challenges and limited productivity.

Innovation Solution

A multifunctional handler system with separate loading, sorting, and testing sections, connected to a host computer, allowing independent operation, 'first in, first out' tray sequencing, and a thermally controlled test chamber with multiple spaces and pipelines for temperature management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the test chamber part is integrated with the loading and sorting and unloading units, then the structure is compact, but the operation of the whole handler system stops when either part is out of order and repairs are difficult

Engineering Contradiction:
Improvestructural integrationVSAvoidsystem continuity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the handler system into separate functional modules: a test chamber module and a loading/sorting/unloading module. This segmentation allows independent operation and maintenance of each module, so that failures in one module do not necessarily stop the entire system, thereby improving reliability while maintaining structural organization.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the test chamber part has a faster processing speed than the loading and sorting and unloading units, then the test efficiency can be enhanced, but the operation is limited by the slower loading and sorting units

Engineering Contradiction:
Improvetest efficiencyVSAvoidwaiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary actions by having the loading unit prepare and load trays into the test chamber in advance, and the sorting unit prepare sorting positions before testing completes. This allows the test chamber to operate at its full speed without waiting for loading or sorting operations, eliminating waiting time and maximizing test efficiency.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If a number of semiconductor devices are tested in the test chamber, then the test capacity increases, but a constant temperature cannot be maintained due to heat generated by the devices

Engineering Contradiction:
Improvetest capacityVSAvoidtemperature stability
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent introduces an intermediary thermal management system between the semiconductor devices and the test chamber environment. This includes heat dissipation structures and temperature control mechanisms that actively manage the heat generated by multiple devices during testing, maintaining constant temperature conditions even at high test capacities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7838790B2Multifunctional handler system for electrical testing of semiconductor devices
Publication Date: 2010.11.23 SAMSUNG ELECTRONICS CO LTD
  • US7838790B2 patent drawing
  • US7838790B2 patent drawing
  • US7838790B2 patent drawing

AI summary

A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.