Hanging Die Package With Nested Substrate Mounting
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Solution Overview
Problem
The semiconductor arts face challenges in integrating electronic functionality into a small volume, particularly in packaging electronic components to achieve incremental improvements in packing density of electronic devices.
Innovation Solution
A semiconductor die package design that incorporates multiple hanging dies mounted to the underside of a substrate with direct I/O communication and conductive plugs, utilizing a land grid array and through-silicon vias to minimize height and enhance communication, while allowing for proper reflow of solder balls during attachment to a planar board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple hanging dies are mounted to the underside of a substrate, then packing density is improved, but vertical space requirements increase
Solution Approach 1:
The patent implements a nested arrangement where a first hanging die is positioned vertically between the substrate and a second hanging die. This nesting configuration allows multiple dies to occupy overlapping vertical spaces, effectively increasing packing density without proportionally increasing the overall vertical profile of the package.
Solution Approach 2:
The patent transitions from a traditional single-plane die arrangement to a multi-dimensional configuration by mounting dies on both the top and underside of the substrate, and by stacking hanging dies vertically. This dimensional change enables more efficient space utilization and improves packing density while managing vertical constraints.
2Length of stationary object
If hanging dies are mounted close to the substrate, then vertical profile is reduced, but solder ball reflow space is limited
Solution Approach 1:
The patent applies different spacing strategies to different regions of the package. The first hanging die is positioned close to the substrate to minimize vertical profile, while the second hanging die is positioned farther away to provide adequate space for solder ball reflow. This localized quality differentiation resolves the contradiction between compactness and manufacturability.
3Device complexity
If direct I/O communication is implemented between hanging dies and substrate, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs through-silicon vias (TSVs) that are pre-formed during the die fabrication process, establishing direct I/O communication pathways before the dies are mounted to the substrate. This preliminary action simplifies the overall communication architecture by eliminating the need for complex wire bonds or interconnect structures, while the precision requirements are managed through standardized TSV fabrication processes.
Data Source
AI summary
An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.