Hardened RISC-V Custom Instruction Queues for Accelerator Waits
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Solution Overview
Problem
Existing RISC-V processors experience high latency when waiting for responses from custom accelerators, impacting performance and boot-up time, especially in secure boot implementations, and require complex design updates for clock domain crossing.
Innovation Solution
A system and method for queuing custom instructions in a hardened processor, using memory systems to buffer operations and responses, allowing blocking and non-blocking implementations without RTL updates, and facilitating clock domain crossing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If custom instructions are executed directly without queuing mechanism, then the processor can execute instructions sequentially, but the processor experiences high latency and idle time while waiting for responses from custom accelerators
Solution Approach 1:
The patent implements a queueing mechanism where custom instructions are buffered in memory before being transmitted to the custom accelerator. This allows the processor to prepare and queue multiple instructions in advance, then retrieve results from the queue without waiting for the accelerator to complete each instruction sequentially, thereby reducing latency and improving productivity
Solution Approach 2:
The patent introduces a queue as an intermediary component between the processor and the custom accelerator. This queue acts as a buffer that decouples the processor from the accelerator, allowing the processor to continue executing other instructions while the accelerator processes queued commands in the background, thus eliminating the idle waiting time
2Speed
If clock domain crossing is implemented between high frequency processor and lower frequency custom accelerator, then timing gaps can be closed, but the design complexity increases
Solution Approach 1:
The patent uses the queue as an intermediary that spans across different clock domains. The queue is designed to be accessible from both the high-frequency processor domain and the lower-frequency accelerator domain, providing a simplified interface that handles clock domain crossing without requiring complex synchronization mechanisms or timing gap closure techniques
3Reliability
If blocking implementation is used for custom instruction queuing, then the processor can wait for accelerator response, but the processor cannot execute other instructions during the wait time
Solution Approach 1:
The patent implements a dynamic queuing system that can operate in different modes (blocking and non-blocking) based on the specific instruction requirements. The queueing mechanism allows the processor to choose whether to wait for confirmation of instruction completion or to continue executing other instructions, providing flexibility that maintains both reliability and productivity
Data Source
AI summary
The present invention relates to a system and method for queuing in custom instruction extension of a hardened processor (203) such as a RISC-V processor implemented on a System-on-Chip (SoC) fabric; which enables high performance for said RISC-V processor (203) when interacting with any custom accelerator (205) via custom instruction extension (207) due to the reduced latency in waiting for a response from said custom accelerator (205). The system and method of the present invention also facilities clock domain crossing between the high frequency hardened processor (203) and the lower frequency custom accelerator (205), thus simplifying the design requirements for the custom accelerator (205) to close the timing gap. Besides that, the system and method of the present invention also supports blocking and non-blocking implementations of the queueing capability without needing for updates to the register transfer level (RTL) design.