Hardware Accelerator Data Grouping and Compression for Ordered Memory Access

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Solution Overview

Problem

Existing data processing methods for hardware accelerators face inefficiencies due to improper data input/output design, leading to increased processing time and reduced memory utilization, particularly when dealing with multi-dimensional arrays.

Innovation Solution

A method of grouping and compressing elements of the output array, along with a scheduling technology for loading data in a DRAM, where elements are read and input in a specific order to optimize data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is stored and read in conventional order without grouping, then memory access is simple, but processing time increases and memory utilization decreases

Engineering Contradiction:
Improveprocessing timeVSAvoiddata management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides the output array into multiple data groups along the first direction of dimension, where each data group contains elements with the same row index. This segmentation allows the hardware accelerator to process and store data in manageable units, improving processing time while maintaining manageable complexity through structured organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control part performs preliminary grouping and compression of output data before storing it in memory. By pre-organizing data into data groups and compressing them according to the defined structure, the system reduces processing time during subsequent reads without requiring complex real-time management operations

Inventive Principle:
Principle #10Preliminary action

2Productivity

If data is read sequentially without specific ordering, then memory access is straightforward, but data processing efficiency decreases

Engineering Contradiction:
Improvedata processing efficiencyVSAvoiddata input/output operation
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent implements dynamic data reading strategies where the control part determines the optimal reading order based on the computational graph dependencies. The system can read data groups sequentially along the first direction or along the second direction depending on what is needed for the next computation step, making the operation adaptable rather than fixed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control part receives feedback about which data groups are needed for subsequent computations and adjusts the reading order accordingly. This feedback mechanism ensures that data is read in the most efficient sequence, improving processing efficiency while the control logic handles the complexity of ordering automatically

Inventive Principle:
Principle #23Feedback

3Productivity

If additional buffers are added to improve data processing, then continuous data input/output is enabled, but device complexity and memory space requirements increase

Engineering Contradiction:
Improvecontinuous data processing capabilityVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the internal memory serve multiple functions: it stores compressed data groups, manages data for multiple computational steps, and provides buffering capabilities. By making the memory system multi-functional for data management, the system achieves continuous processing capability without adding separate dedicated buffers, thus avoiding increased device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the buffering function with the existing memory storage structure. Instead of adding separate buffers for data management, the system merges buffering capabilities into the data group storage mechanism, where data groups are stored and managed as a unified structure that provides both storage and buffering functions

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250231808A1Method for storing output data of hardware accelerator in memory, method for reading input data of hardware accelerator from memory, and hardware accelerator therefor
Publication Date: 2025.07.17 OPENEDGES TECH INC
  • US20250231808A1 patent drawing
  • US20250231808A1 patent drawing
  • US20250231808A1 patent drawing

AI summary

Disclosed is a data processing method of sequentially reading a plurality of non-compressed data groups or a plurality of compressed data groups corresponding to each of the non-compressed data groups from a memory by taking priority in a first direction of dimension over a second direction of dimension of an input array, when it is determined that the elements should be sequentially input to the data operation part by taking priority in the first direction of dimension over the second direction of dimension.