Hardware-Assisted Guest Address Space Scanning in Virtualized Systems
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Solution Overview
Problem
Modern hypervisors face challenges in optimizing second-stage page tables to reduce TLB pressure and memory usage, as scanning first-stage page tables is a slow process that involves complex algorithms, leading to potential VM pauses.
Innovation Solution
A method is introduced where a hypervisor scans a guest virtual address space by executing an address translation instruction on a processor, reading registers to determine errors, and adjusting the current GVA based on faulting page tables, leveraging hardware-assisted scanning to avoid software-based page walkers and reduce VM pauses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hypervisor walks first stage page tables to optimize second stage page tables, then TLB pressure is reduced and memory usage is reduced, but the scanning process is slow and causes VM pauses
Solution Approach 1:
The patent replaces the software-based page table walking mechanism with a hardware-assisted scanning approach. The processor's address translation hardware (MMU and TLB) is leveraged to perform the scanning operation, substituting the manual software traversal with automated hardware-driven address translation. This substitution enables the hypervisor to efficiently scan guest virtual address spaces without causing VM pauses, as the hardware performs the scanning in the background during normal address translation operations.
2Reliability
If software-based page walkers are used to scan guest virtual address spaces, then second stage page tables can be optimized, but the process involves complex algorithms and reduces performance
Solution Approach 1:
The patent implements a self-service mechanism where the processor's own address translation hardware is used to perform the scanning operation. Instead of requiring external software-based page walkers with complex algorithms, the MMU and TLB automatically scan the guest virtual address space as part of their normal address translation function. The hypervisor simply needs to set up the initial conditions and enable hardware-assisted scanning, after which the hardware autonomously performs the scanning and reports results, eliminating the need for complex software algorithms.
3Productivity
If hardware-assisted scanning is used to scan guest virtual address spaces, then VM pauses are reduced and scanning efficiency is improved, but requires leveraging architectural TLBs
Solution Approach 1:
The patent exploits the multi-functionality of the processor's address translation hardware. The MMU and TLB, which are already present and necessary for normal address translation operations, are made to serve an additional function: scanning the guest virtual address space. By configuring the hardware to perform both address translation and scanning operations, the system achieves high scanning efficiency without adding dedicated scanning hardware. The same architectural TLBs that are already part of the processor design are leveraged to cache and translate addresses during the scanning process.
Data Source
AI summary
An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.